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Start Over Author "Yuuichi Hirano" Journal 2000 symposium on vlsi technology. digest of technical papers (cat. no.00ch37104)
1 results on '"Yuuichi Hirano"'

1. Impact of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications

Author

Takuji Matsumoto, K. Yamamoto, T. Iwamatsu, S. Maeda, Yoshiki Wada, Yutaro Yamaguchi, Yuuichi Hirano, Masahide Inuishi, H. Komurasaki, S. Maegawa, T. Ipposhi, Kimio Ueda, and Koichiro Mashiko

Subjects
Inductance, Engineering, Passivation, CMOS, business.industry, Shallow trench isolation, MOSFET, Trench, Electrical engineering, Silicon on insulator, Optoelectronics, System on a chip, business
Abstract

In this paper, for the first time, we propose a 0.18/spl mu/m SOI CMOS using hybrid trench isolation with high resistivity substrates (HRS) and reveal its impact on high performance embedded RF/analog applications, which is essential for "system on a chip (SOC)". The hybrid trench isolation is a type of partial trench isolation which serves scalable body-tied SOI MOSFETs, and full trench isolation which provides high quality passives associated with the HRS. Using this technology, the advantages of SOI MOSFETs are quantitatively proven. Excellent body-fixing capability of this SOI MOSFET, and high-quality on-chip inductance is demonstrated for RF/analog LSIs. For mixed-signal configurations, superior CMOS performance is demonstrated.

Published
2002

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