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A research project, in which various high-density interconnect (HDI) and wafer-scale integration (WSI) implementation variants of a common computer architecture, the associative string processor (ASP), are compared, is discussed. The ASP is a fault-tolerant and highly versatile massively parallel processor capable of sustaining high performance over a wide range of computationally intensive tasks and, unlike most other computer architectures, the ASP has been designed to exploit state-of-the-art microelectronic technology. The study indicates that, until the feasibility of WSI ASP technology has been proven, a 3-D HDI ASP seems to offer a cost-effective alternative technology for the development of highly compact massively parallel processors for aerospace and automotive applications. >

The WSI associative string processor (WASP), a massively parallel processor, implemented as a system-on-silicon, is discussed. The WASP is organized as a string of simple content-addressable associative processing elements (APEs), which achieves particularly high APE packing density and incorporates a highly flexible and compact inter-APE communications network on silicon. At the VLSI level the associative string processor architecture is already finding wide acceptance in a variety of applications areas. The integration of this architecture with the potential of wafer-scale integration (WSI) promises further significant decreases in size and weight production cost, and power dissipation, combined with improvements in performance and reliability. The WASP architecture and microelectronic implementation are described. The evolution of the WASP research program, the current WASP demonstrators, and the potential characteristics of a realistic WASP system are summarized. >