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The increasing heterogeneity and complexity of VLSI systems has made the use of C++ popular for building simulation and synthesis models at higher levels of abstraction. Currently, there are several different embodiments of C++ based environments, mostly in the form of hardware modeling libraries built on top of C++. However, the semantic gap between hardware modeling concepts, and the software programming language constructs, poses several issues which require critical examination. In this paper, we address the issue of interoperability between models built using different C++ based modeling libraries, or even modeling "styles" including home-grown C++ models. Model interoperability is the ability to use C++ based descriptions across different C++ based modeling environments. Two important aspects of interoperability are model composability, and model reusability. In this paper we focus on model reusability, analyzing various dimensions of the re usability of C++ based models, in an integration environment for building SOC models. We show how an inheritance based composition may be used to make two distinct C++ based class libraries interoperate. We also outline the implementation of a dynamic composition environment, which allows automatic run-time delegation based composition, to achieve interoperability. These strategies allow system integrators to focus on design composition, rather than software programming details inherent in the current inheritance based solutions.