34 results on '"Mark Kassab"'
Search Results
2. Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels.
3. Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations.
4. Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs.
5. Effective Design of Layout-Friendly EDT Decompressor.
6. TEA: A Test Generation Algorithm for Designs with Timing Exceptions.
7. Efficient Prognostication of Pattern Count with Different Input Compression Ratios.
8. Hybrid Hierarchical and Modular Tests for SoC Designs.
9. Using dynamic shift to reduce test data volume in high-compression designs.
10. Isometric test compression with low toggling activity.
11. Test Compression Improvement with EDT Channel Sharing in SoC Designs.
12. EDT bandwidth management - Practical scenarios for large SoC designs.
13. A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores.
14. EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism.
15. Low capture power at-speed test in EDT environment.
16. Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains.
17. Dynamic channel allocation for higher EDT compression in SoC designs.
18. At-speed scan test with low switching activity.
19. Test Generation for Designs with On-Chip Clock Generators.
20. Low Power Scan Shift and Capture in the EDT Environment.
21. Test Generation for Timing-Critical Transition Faults.
22. Test Generation in the Presence of Timing Exceptions and Constraints.
23. X-Press Compactor for 1000x Reduction of Test Data.
24. OCI: Open Compression Interface.
25. Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects.
26. At-Speed Testing with Timing Exceptions and Constraints-Case Studies.
27. Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model.
28. Realizing High Test Quality Goals with Smart Test Resource Usage.
29. Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions.
30. Embedded Deterministic Test for Low-Cost Manufacturing Test.
31. Logic BIST for large industrial designs: real issues and case studies.
32. A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance.
33. Hierarchical Functional-Fault Simulation for High-Level Synthesis.
34. Software Accelerated Functional Fault Simulation for Data-Path Architectures.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.