26 results on '"Kyung-A Son"'
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2. High-Efficiency and High-Reliability Deep-UV Light-Emitting Diodes Using Transparent Ni-Implanted AlN Ohmic Electrodes.
3. A 0.42-3.45 Gb/s Referenceless Clock and Data Recovery Circuit With Counter-Based Unrestricted Frequency Acquisition.
4. A 2.41-pJ/bit 5.4-Gb/s Dual-Loop Reference-Less CDR With Fully Digital Quarter-Rate Linear Phase Detector for Embedded DisplayPort.
5. HisVA: A Visual Analytics System for Studying History.
6. Phase-change RF switches with robust switching cycle endurance.
7. A low jitter burst-mode clock and data recovery circuit with two symmetric VCO's.
8. On-chip jitter tolerance measurement technique for CDR circuits.
9. Indoor positioning of mobile devices with agile iBeacon deployment.
10. A 8.7mW 5-Gb/s clock and data recovery circuit with 0.18-µm CMOS.
11. A Two-Step Time-to-Digital Converter using Ring Oscillator Time Amplifier.
12. Eye-open monitor using two-dimensional counter value profile.
13. Design of a third-order delta-sigma TDC with error-feedback structure.
14. A 200-Mb/s to 3-Gb/s wide-band referenceless CDR using bidirectional frequency detector.
15. Correlation Canceling-Type Feedback Canceler Based on Decision-Directed Pilot Symbols for T-DMB Repeaters.
16. Performance of Feedback Cancellers for T-DMB On-Channel Repeaters.
17. Noise-robust channel estimation for DVB-T fixed receptions.
18. A Statistical Approach to the Estimation of Delay Dependent Switching Activities in CMOS Combinational Circuits.
19. A 200 Mb/s∼3.2 Gb/s referenceless clock and data recovery circuit with bidirectional frequency detector.
20. Postprocessing With Wiener Filtering Technique for Reducing Residual Crosstalk in Blind Source Separation.
21. New edge-enhanced error diffusion algorithm based on the error sum criterion.
22. A burst-mode clock and data recovery circuit with two symmetric quadrature VCO's.
23. Precise time-difference repetition for TDC with delay mismatch cancelling scheme.
24. On-chip jitter tolerance measurement technique with independent jitter frequency modulation from VCO in CDR.
25. A low-power CDR using dynamic CML latches and V/I converter merged with XOR for half-rate linear phase detection.
26. A 1.1 mW/Gb/s 10 Gbps half-rate clock-embedded transceiver for high-speed links in 65 nm CMOS.
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