161 results on '"Vrudhula, Sarma"'
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2. First Demonstration of Reconfigurable Threshold Logic Gate using FeFET
3. An ASIC Accelerator for QNN With Variable Precision and Tunable Energy-Efficiency
4. Evidence of transport degradation in 22 nm FD-SOI charge trapping transistors for neural network applications
5. An ASIC Accelerator for QNN with Variable Precision and Tunable Energy-Efficiency
6. An ASIC Accelerator for QNN with Variable Precision and Tunable Energy-Efficiency
7. A Novel Pseudo-Flash Based Digital Low Dropout (LDO) Voltage Regulator
8. A New Approach to Clock Skewing for Area and Power Optimization of ASICs using Differential Flipflops and Local Clocking
9. A Mixed-Signal Quantized Neural Network Accelerator Using Flash Transistors
10. Evidence of Transport Degradation in 22 Nm Fd-Soi Charge Trapping Transistors for Neural Network Applications
11. Tunable Precision Control for Approximate Image Filtering in an In-Memory Architecture with Embedded Neurons
12. EdgeWise: Energy-efficient CNN Computation on Edge Devices under Stochastic Communication Delays
13. A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells
14. Heterogeneous FPGA Architecture Using Threshold Logic Gates for Improved Area, Power, and Performance
15. A Flash-based Current-mode IC to Realize Quantized Neural Networks
16. CIDAN-XE: Computing in DRAM with Artificial Neurons
17. CAMDNN: Content-Aware Mapping of a Network of Deep Neural Networks on Edge MPSoCs
18. CIDAN: Computing in DRAM with Artificial Neurons
19. Energy-Efficient Mapping for a Network of DNN Models at the Edge
20. A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells
21. Enabling Incremental Knowledge Transfer for Object Detection at the Edge
22. Performance Modeling for CNN Inference Accelerators on FPGA
23. A Statistical Methodology for Post-Fabrication Weight Tuning in a Binary Perceptron
24. Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators
25. ELSA
26. Optimizing User Satisfaction of Mobile Workloads Subject to Various Sources of Uncertainties
27. An Energy-Efficient Reconfigurable LSTM Accelerator for Natural Language Processing
28. Edge Valued Binary Decision Diagrams
29. Techniques for Estimating Test Length Under Random Test
30. Embedding Binary Perceptrons in FPGA to improve Area, Power and Performance
31. Threshold Logic in a Flash
32. An Energy-Efficient FPGA Implementation of an LSTM Network Using Approximate Computing
33. Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs
34. FPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, Power and Area
35. Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA
36. ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler
37. DORA: Optimizing Smartphone Energy Efficiency and Web Browser Performance under Interference
38. An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks
39. A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits
40. End-to-end scalable FPGA accelerator for deep residual networks
41. Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks
42. Statistical library characterization using arbitrary polynomial chaos
43. Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops
44. High-performance face detection with CPU-FPGA acceleration
45. Improving smartphone user experience by balancing performance and energy with probabilistic QoS guarantee
46. Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks
47. On-Chip Sparse Learning Acceleration With CMOS and Resistive Synaptic Devices
48. Mitigating effects of non-ideal synaptic device characteristics for on-chip learning
49. Thermal aware floorplanning incorporating temperature dependent wire delay estimation
50. Fully parallel write/read in resistive synaptic array for accelerating on-chip learning
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