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4. Enabling Technologies II: CONSENS Tools

5. Advances in SiCN-SiCN Bonding with High Accuracy Wafer-to-Wafer (W2W) Stacking Technology

8. Demonstration of a novel low cost single material temporary bond solution for high topography substrates based on a mechanical wafer debonding and innovative adhesive removal

12. Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques

13. Barrier and seed repair performance of thin RuTa films for Cu interconnects

16. Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance

17. Self Aligned CuGeN Process for 32/22nm Nodes and Beyond

18. Performance improvement of tall triple gate devices with strained SiN layers

20. Process Optimization and Integration of Trimethylsilane-Deposited α-SiC:H and α-SiCO:H Dielectric Thin Films for Damascene Processing

21. Characterisation and integration feasibility of JSR’s low-k dielectric LKD-5109

25. Integration feasibility of porous SiLK* semiconductor dielectric

27. Characterization and Integration in Cu Damascene Structures of AURORA, an Inorganic Low-k Dielectric

45. Ge deep sub-micron pFETs with etched TaN metal gate on a high-k dielectric, fabricated in a 200mm silicon prototyping line

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