43 results on '"Sebaai, F."'
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2. Forksheet FETs with Bottom Dielectric Isolation, Self-Aligned Gate Cut, and Isolation between Adjacent Source-Drain Structures
3. FinFETs with Thermally Stable RMG Gate Stack for Future DRAM Peripheral Circuits
4. Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails
5. A Novel Ni-Al Alloy Metal Induced Lateral Crystallization Process for Improved Channel Conduction in 3-D NAND Flash
6. Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections
7. High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories
8. Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails
9. Buried Power Rail Metal exploration towards the 1 nm Node
10. Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond
11. First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers
12. Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node
13. Integration of Ruthenium-based Wordline in a 3-D NAND Memory Devices
14. Vertical Nanowire and Nanosheet FETs: Device Features, Novel Schemes for Improved Process Control and Enhanced Mobility, Potential for Faster & More Energy Efficient Circuits
15. Scaled, Novel Effective Workfunction Metal Gate Stacks for Advanced Low-VT, Gate-All-Around Vertically Stacked Nanosheet FETs with Reduced Vertical Distance between Sheets
16. High performance strained Germanium Gate All Around p-channel devices with excellent electrostatic control for sub-Jtlnm LG
17. 12-EUV Layer Surrounding Gate Transistor (SGT) for Vertical 6-T SRAM: 5-nm-class Technology for Ultra-Density Logic Devices
18. Vertical Ferroelectric HfO2 FET based on 3-D NAND Architecture: Towards Dense Low-Power Memory
19. First Demonstration of Vertically Stacked Gate-All-Around Highly Strained Germanium Nanowire pFETs
20. DTCO and TCAD for a 12 Layer-EUV Ultra-Scaled Surrounding Gate Transistor 6T-SRAM
21. First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETs
22. An In-depth Study of High-Performing Strained Germanium Nanowires pFETs
23. Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition
24. CMOS Integration of Thermally Stable Diffusion and Gate Replacement (D&GR) High-k/Metal Gate Stacks in DRAM Periphery Transistors
25. Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition
26. N5 technology node dual-damascene interconnects enabled using multi patterning
27. In Depth Analysis of 3D NAND Enablers in Gate Stack Integration and Demonstration in 3D Devices
28. Modeling of tone inversion process flow for N5 interconnect to characterize block tip to tip
29. Spin-on metal oxide materials for N7 and beyond patterning applications
30. Scalability of InGaAs gate-all-around FET integrated on 300mm Si platform: Demonstration of channel width down to 7nm and Lg down to 36nm
31. Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow
32. Oxygen Control Challenge for Advanced Wet Processing
33. (Invited) Selective Etch of Si and SiGe for Gate All-Around Device Architecture
34. Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal
35. RMG nMOS 1st process enabling 10x lower gate resistivity in N7 bulk FinFETs
36. An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates
37. Thermal and Plasma Treatments for Improved (Sub-)1nm EOT Planar and FinFET-based RMG High-k Last Devices and Enabling a Simplified Scalable CMOS Integration Scheme
38. Selective Ni Removal Deposited on Ge at Different Annealing Temperatures
39. Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks
40. W vs. Co-Al as Gate Fill-Metal for Aggressively Scaled Replacement High-k/Metal Gate Devices for (Sub-)22nm Tech. Nodes
41. Effective Work Function Engineering for Aggressively Scaled Planar and FinFET-based Devices with High-k Last Replacement Metal Gate Tech.
42. Process control & integration options of RMG technology for aggressively scaled devices
43. Single-Metal Dual-Dielectric (SMDD) gate-first CMOS integration towards low VT and high performance
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