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49 results on '"Mitsuhashi, R."'

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7. Gate Leakage Advantage of LaO Incorporation for Vt Tuning in High-k nMOSFETs over Metal Gate WF Control

10. Achieving low-VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack

11. Reliability study of La2O3 capped HfSiON high-permittivity n-type metal-oxide-semiconductor field-effect transistor devices with tantalum-rich electrodes

12. Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay

13. Cost-Effective Low $V_{t}$ Ni-FUSI CMOS on SiON by Means of Al Implant (pMOS) and $\hbox{Yb}{+}\hbox{P}$ Coimplant (nMOS)

14. Low VT CMOS using doped Hf-based oxides, TaC-based Metals and Laser-only Anneal

15. Demonstration of Metal-Gated Low $V_{t}$ n-MOSFETs Using a Poly-$\hbox{Si/TaN/Dy}_{2}\hbox{O}_{3}/\hbox{SiON}$Gate Stack With a Scaled EOT Value

16. Achieving 9ps unloaded ring oscillator delay in FuSI/HfSiON with 0.8 nm EOT

17. Strain enhanced FUSI/HfSiON Technology with optimized CMOS Process Window

18. Low Vt Ni-FUSI CMOS Technology using a DyO cap layer with either single or dual Ni-phases

19. Nitrogen Profile and Dielectric Cap Layer (Al2O3, Dy2O3, La2O3) Engineering on Hf-Silicate

20. Optimization of HfSiON using a design of experiment (DOE) approach on 0.45V Vt Ni-FUSI CMOS transistors

21. A Dy2O3-capped HfO2 Dielectric and TaCx-based Metals Enabling Low-Vt Single-Metal-Single-Dielectric Gate Stack

22. Oxygen-Vacancy-Induced Vt shift in La-containing Devices

23. Achieving low VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack

24. Ni-based FUSI gates: CMOS Integration for 45nm node and beyond

28. 65nm-node Low-Standby-Power FETs with HfAlOx Gate Dielectric

48. Ni-FUSI on high-k as a candidate for 65nm LSTP CMOS

49. Low Power CMOS Featuring Dual Work Function FUSI on HfSiON and 17ps Inverter Delay

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