45 results on '"King-Liu, Tsu-Jae"'
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2. 3D Integrated CMOS-NEM Systems: Enabling Next-Generation Computing Technology
3. Tuning of Schottky barrier height using oxygen-inserted (OI) layers and fluorine implantation
4. A Density Metric for Semiconductor Technology [Point of View]
5. Study of Poly-SiGe Structural Properties for Modularly Integrated MEMS
6. Mechanical Properties of Polycrystalline Silicon formed by Al-2%Si Induced Crystallization
7. Reducing adhesion energy of nano-electro-mechanical relay contacts by self-assembled Perfluoro (2,3-Dimethylbutan-2-ol) coating
8. Tilted ion implantation of spin-coated SiARC films for sub-lithographic and two-dimensional patterning
9. Changes to the Editorial Board
10. Changes to the Editorial Board
11. Tilted ion implantation as a cost-efficient sublithographic patterning technique
12. Changes to the Editorial Board
13. Changes to the Editorial Board
14. Changes to the Editorial Board
15. Electron mobility enhancement in (100) oxygen-inserted silicon channel
16. Mechanically modulated tunneling resistance in monolayer MoS2
17. 2.5 GB/s germanium gate photoMOSFET integrated to silicon photonics
18. Rapid melt grown germanium gate photoMOSFET on a silicon waveguide
19. Editorial
20. Reliability of MEM relays for zero leakage logic
21. Scaled Micro-Relay Structure with Low Strain Gradient for Reduced Operating Voltage
22. Highly scaled (Lg∼56nm) gate-last Si tunnel field-effect transistors with ION>100μA/μm
23. Steep-subthreshold-slope devices on SOI
24. Study of Random Dopant Fluctuation Effects in Germanium-Source Tunnel FETs
25. Collaborative research on emerging technologies and design
26. Mechanical Computing Redux: Relays for Integrated Circuit Applications
27. Comparative Study of FinFET Versus Quasi-Planar HTI MOSFET for Ultimate Scalability
28. Prospects for MEM logic switch technology
29. Sub-60nm Si tunnel field effect transistors with Ion >100 µA/µm
30. Tri-gate bulk CMOS technology for improved SRAM scalability
31. Seesaw Relay Logic and Memory Circuits
32. SRAM Read/Write Margin Enhancements Using FinFETs
33. Analysis of the relationship between random telegraph signal and negative bias temperature instability
34. The Effect of Random Dopant Fluctuation on Specific Contact Resistivity
35. Characterization of Nanometer-Scale Gap Formation
36. Study of Germanium Epitaxial Recrystallization on Bulk-Si Substrates
37. Nano-Electro-Mechanical Nonvolatile Memory (NEMory) Cell Design and Scaling
38. SRAM yield and performance enhancements with tri-gate bulk MOSFETs
39. Impact of gate line edge roughness on double-gate FinFET performance variability
40. Optimization of Flash Annealing Parameters to Achieve Ultra-Shallow Junctions for sub-45nm CMOS
41. Dual-Bit Gate-Sidewall Storage FinFET NVM and New Method of Charge Detection
42. Intrinsic Advantages of SOI Multiple-Gate MOSFET (MuGFET) for Low Power Applications
43. Characterization of Polycrystalline Silicon-Germanium Film Deposition for Modularly Integrated MEMS Applications
44. Selective Enhancement of SiO[sub 2] Etch Rate by Ar-Ion Implantation for Improved Etch Depth Control
45. ALD Refill of Nanometer-Scale Gaps with High-κ Dielectric for Advanced CMOS Technologies
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