1. 13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process
- Author
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Choi, Ikjoon, primary, Hong, Seunghwan, additional, Kim, Kihyun, additional, Hwang, Jeong-Sik, additional, Woo, Seunghan, additional, Kim, Young-Sang, additional, Cho, Cheong-Ryong, additional, Lee, Eun-Young, additional, Lee, Hun-Jae, additional, Jung, Min-Su, additional, Jung, Hee-Yun, additional, Hwang, Ju-Seong, additional, Yoon, Junsub, additional, Lim, Wonmook, additional, Yoo, Hyeong-Jin, additional, Lee, Won-Ki, additional, Oh, Jung-Kyun, additional, Lee, Dong-Su, additional, Lee, Jong-Eun, additional, Kim, Jun-Hyung, additional, Kim, Young-Kwan, additional, Park, Su-Jin, additional, Ho, Byung-Kyu, additional, Na, Byong-Wook, additional, Choi, Hye-In, additional, Lee, Chung-Ki, additional, Lee, Soo-Jung, additional, Shin, Hyunsung, additional, Lee, Young-Kyu, additional, Ryu, Jang-Woo, additional, Shin, Sangwoong, additional, Park, Sungchul, additional, Lim, Daihyun, additional, Bae, Seung-Jun, additional, Sohn, Young-Soo, additional, Oh, Tae-Young, additional, and Hwang, SangJoon, additional
- Published
- 2024
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