258 results on '"Horiguchi, N"'
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2. CMOS Scaling by Nanosheet Device Architectures and Backside Engineering
3. Towards Improved Nanosheet-Based Complementary Field Effect Transistor (CFET) Performance Down to 42nm Contacted Gate Pitch
4. Forksheet Field-Effect Transistors for Area Scaling and Gate-Drain Capacitance Reduction in Nanosheet-based CMOS Technologies
5. Characterization and Advanced Modeling of Dielectric Defects in Low-Thermal Budget RMG MOSFETs Using 1/f Noise Analysis
6. Compact thermally stable high voltage FinFET with 40 nm tox and lateral break-down >35 V for 3D NAND flash periphery application
7. 3D Stacked Devices and MOL Innovations for Post-Nanosheet CMOS Scaling
8. Ultimate Layer Stacking Technology for High Density Sequential 3D Integration
9. Integration of a Stacked Contact MOL for Monolithic CFET
10. Novel Low Thermal Budget CMOS RMG: Performance and Reliability Benchmark Against Conventional High Thermal Budget Gate Stack Solutions
11. Molybdenum Nitride as a Scalable and Thermally Stable pWFM for CFET
12. Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning
13. Reliability challenges in Forksheet Devices: (Invited Paper)
14. Forksheet FETs with Bottom Dielectric Isolation, Self-Aligned Gate Cut, and Isolation between Adjacent Source-Drain Structures
15. Insights into Scaled Logic Devices Connected from Both Wafer Sides
16. Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells
17. Low thermal budget PBTI and NBTI reliability solutions for multi-Vth CMOS RMG stacks based on atomic oxygen and hydrogen treatments
18. Low temperature source/drain epitaxy and functional silicides: essentials for ultimate contact scaling
19. FinFETs with Thermally Stable RMG Gate Stack for Future DRAM Peripheral Circuits
20. Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails
21. Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling
22. Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections
23. High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories
24. Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails
25. Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO
26. Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery
27. Evaluating Forksheet FET Reliability Concerns by Experimental Comparison with Co-integrated Nanosheets
28. Inspection and metrology challenges for 3 nm node devices and beyond
29. Dipole-First Gate Stack as a Scalable and Thermal Budget Flexible Multi-Vt Solution for Nanosheet/CFET Devices
30. Comparison of Electrical Performance of Co-Integrated Forksheets and Nanosheets Transistors for the 2nm Technological Node and Beyond
31. Low-temperature atomic and molecular hydrogen anneals for enhanced chemical $\mathbf{SiO}_{2}$ IL quality in low thermal budget RMG stacks
32. Buried Power Rail Metal exploration towards the 1 nm Node
33. Novel low thermal budget gate stack solutions for BTI reliability in future Logic Device technologies : Invited paper
34. Reliability of Barrierless PVD Mo
35. Process Integration of High Aspect Ratio Vias with a Comparison between Co and Ru Metallizations
36. Combining TCAD and advanced metrology techniques to support device integration towards N3
37. Disruptive Technology Elements, and Rapid and Accurate Block-Level Performance Evaluation for 3nm and Beyond
38. Nanosheet FETs and their Potential for Enabling Continued Moore's Law Scaling
39. Reliability of a DME Ru Semidamascene scheme with 16 nm wide Airgaps
40. Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips
41. Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond
42. Toward high-performance and reliable Ge channel devices for 2 nm node and beyond
43. Atomic Hydrogen Exposure to Enable High-Quality Low-Temperature SiO2 with Excellent pMOS NBTI Reliability Compatible with 3D Sequential Tier Stacking
44. FinFETs and Their Futures
45. Nanowire & Nanosheet Fets for Advanced Ultra-Scaled, High-Density Logic and Memory Applications
46. Addressing Key Challenges for SiGe-pFin Technologies: Fin Integrity, Low-DIT Si-Cap-Free Gate Stack and Optimizing the Channel Strain
47. Overview of Bias Temperature Instability in Scaled DRAM Logic for Memory Transistors
48. First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers
49. Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node
50. 3D Sequential Low Temperature Top Tier Devices using Dopant Activation with Excimer Laser Anneal and Strained Silicon as Performance Boosters
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