77 results on '"Flottes, Marie-Lise"'
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2. Hybrid Protection of Digital FIR Filters
3. Resynthesis-based Attacks Against Logic Locking
4. SKG-Lock+: A Provably Secure Logic Locking SchemeCreating Significant Output Corruption
5. Leveraging Layout-based Effects for Locking Analog ICs
6. Manufacturing Testing and Security Countermeasures
7. Erratum to: SOC Design Methodologies
8. Laser-Induced Fault Effects in Security-Dedicated Circuits
9. On Preventing SAT Attack with Decoy Key-Inputs
10. High-level Intellectual Property Obfuscation via Decoy Constants
11. A New Scan Attack on RSA in Presence of Industrial Countermeasures
12. On Countermeasures Against Fault Attacks on the Advanced Encryption Standard
13. Compression-based SoC Test Infrastructures
14. A Secure Scan Controller for Protecting Logic Locking
15. Power-constrained Test Scheduling for SoCs under a “no session” scheme
16. A Comprehensive Approach to a Trusted Test Infrastructure
17. A Survey on Security Threats and Countermeasures in IEEE Test Standards
18. Logic Locking: A Survey of Proposed Methods and Evaluation Metrics
19. Stream vs block ciphers for scan encryption
20. Providing Confidentiality and Integrity in Ultra Low Power IoT Devices
21. Encryption-Based Secure JTAG
22. Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption
23. Sensitivity to Laser Fault Injection: CMOS FD-SOI vs. CMOS Bulk
24. Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model
25. A New Secure Stream Cipher for Scan Chain Encryption
26. The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks
27. Encryption of test data: which cipher is better?
28. Protection Against Hardware Trojans With Logic Testing: Proposed Solutions and Challenges Ahead
29. SI ECCS: SECure context saving for IoT devices
30. Hacking the Control Flow error detection mechanism
31. Experimentations on scan chain encryption with PRESENT
32. Scan chain encryption for the test, diagnosis and debug of secure circuits
33. Frontside Versus Backside Laser Injection
34. Hardware Trust through Layout Filling: A Hardware Trojan Prevention Technique
35. Using outliers to detect stealthy hardware trojan triggering?
36. Hardware Trojan prevention using layout-level design approach
37. 3D DFT Challenges and Solutions
38. Session-less based thermal-aware 3D-SIC test scheduling
39. On the limitations of logic testing for detecting Hardware Trojans Horses
40. New Testing Procedure for Finding Insertion Sites of Stealthy Hardware Trojans
41. Test Engineering Education in Europe
42. Customized cell detector for laser-induced-fault detection
43. 2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures
44. A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans
45. Layout-aware laser fault injection simulation and modeling: From physical level to gate level
46. Laser attacks on integrated circuits: From CMOS to FD-SOI
47. Built-in self-test for manufacturing TSV defects before bonding
48. Thwarting Scan-Based Attacks on Secure-ICs With On-Chip Comparison
49. Test Versus Security: Past and Present
50. A BIST method for TSVs pre-bond test
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