77 results on '"Chamberlain, S.G."'
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2. High performance a-Si:H thin film transistors based on aluminum gate metallization
3. Fabrication of a-Si:H Tfts at 120°C on Flexible Polyimide Substrates
4. Thick-layered etched-contact amorphous silicon transistors
5. A comparison of the performance and reliability of wet-etched and dry-etched a-Si:H TFTs
6. Compact Spice Modeling and Design Optimization of Low Leakage a-Si:H TFTs for Large-Area Imaging Systems
7. Effect of Nh3/SiH4 Gas Ratios of Top Nitride Layer on Stability and Leakage in a-Si:H Thin Film Transistors
8. Process Integration of A-Si:H Schottky Diode and thin Film Transistor for Low-Energy X-Ray Imaging Applications
9. Improvement of the reliability of amorphous silicon transistors by conduction-band tail width reduction
10. The source-gated amorphous silicon photo-transistor
11. A realistic trap distribution model for numerical simulation of amorphous silicon thin-film transistors and phototransistors
12. The effects of metal-n/sup +/ interface and space charge limited conduction on the performance of amorphous silicon thin-film transistors
13. Drain-induced barrier lowering in buried-channel MOSFET's
14. A numerical model for two-dimensional transient simulation of amorphous silicon thin-film transistors
15. Theory and design methodology for an optimum single-phase CCD
16. Buried-channel MOSFET model for SPICE
17. Analytic and iterative transit-time models for VLSI MOSFETs in strong inversion
18. Output structure for buried-channel CCD
19. Drain-induced barrier-lowering analysis in VSLI MOSFET devices using two-dimensional numerical simulations
20. Piecewise linear CAD model for avalanche photodetectors
21. Modeling and experimental simulation of the low-frequency transfer inefficiency in bucket-brigade devices
22. A multiple-gate CCD-photodiode sensor element for imaging arrays
23. Foreword
24. Accurate two-dimensional simulation of double-beveled p−n junctions
25. MTF Simulation Including Transmittance Effects and Experimental Results of Charge-Coupled Imagers
26. A compact thermal noise model for the investigation of soft error rates in MOS VLSI digital circuits
27. Nonuniform displacement of MOSFET channel pinchoff
28. Experimental confirmation of an analytical model for charge transfer in charge-coupled devices
29. An algorithm for two-dimensional simulation of reverse-biased beveled p−n junctions
30. A model for charge transport in surface channel devices
31. Numerical methods for the charge transfer analysis of charge-coupled devices
32. Modeling and measurement of minority-carrier lifetime versus doping in diffused layers of n+-p silicon diodes
33. MTF simulation including transmittance effects and experimental results of charge-coupled imagers
34. A Multiple-Gate CCD-Photodiode Sensor Element for Imaging Arrays
35. Two-dimensional computer simulation of the breakdown characteristics of a multi-element avalanche photodiode array
36. Three-dimensional simulation of VLSI MOSFET's: The three-dimensional simulation program WATMOS
37. Nonuniform displacement of MOSFET channel pinchoff
38. A calibrated model for the subthreshold operation of a short channel MOSFET including surface states
39. Limitations of multilevel storage in charge-coupled devices
40. Computer model and charge transport studies in short gate charge-coupled devices
41. CHORD: a modular semiconductor device simulation development tool incorporating external network models
42. Spectral Response Limitation Mechanisms of a Shallow Junction n+-p Photodiode
43. Some properties concerning the a.c. impedance of P-I-N and P-N-N+ diodes
44. Short-channel effects on the input stage of surface-channel CCD's
45. Three-dimensional simulation of VLSI MOSFET's: The three dimensional simulation program WATMOS
46. Introduction
47. Novel p-n junction polysilicon dual-gate mosfet for analogue applications
48. A study of the effect of peripheral injection in bipolar transistors using simplified computer analysis
49. A CMOS model for computer-aided circuit analysis and design
50. Design and Realization of a Two-Level 64K Byte CCD Memory System for Microcomputer Applications
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