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This article presents a multi-input piezoelectric energy harvester (PEH) with the multi-input series synchronized switch harvesting on inductor (MIS-SSHI) rectifier and noninterruptive maximum power point tracking (MPPT) technique. The proposed MPPT solution tracks the vibration states of multiple piezoelectric transducers (PZTs) using the fractional cumulative peak voltages method, ensuring the maximum power output for the MIS-SSHI rectifier. In addition, the proposed method captures the peak working voltages of multiple PZTs for MPPT without interrupting the energy harvesting process for open-circuit voltage detection. To validate the effectiveness of this multi-input PEH, an experimental platform is built for performance evaluation. The experiment results confirm the feasibility of the proposed MPPT solution for multi-input rectifiers, achieving a peak MPPT efficiency of up to 98%.

A capacitorless digital low-dropout (D-LDO) voltage regulator with built in adaptive sampling clock is proposed for wireless sensor’s power management applications. The D-LDO regulator adopts a coarse-fine control scheme to accelerate the load transient response. In steady state, the regulator operates at fine-tuning mode with a small switch strength and a low clock frequency. Once the output voltage exceeds the boundaries, a coarse-tuning mode is triggered to quickly find out the desired control bits with a large switch strength and a high clock frequency. The sampling clock is generated with the inherent delay of the internal circuit, thus eliminating the dependence on the external clock. In addition, an active analog-assisted loop is introduced to improve the voltage droop. Fabricated in 180 nm CMOS process, the D-LDO regulator regulates the output voltage range from 0.65 V to 1.15 V. At a VOUT of 0.75 V and VIN of 0.85 V, the proposed D-LDO regulator shows a transient response time of 195 ns with an undershoot of 133 mV at a step load alternating between 5 and 30 mA. It attains a peak current efficiency 99.97% and figure of merit 0.016 ps.

Boolean satisfiability (SAT)-based exact synthesis has made significant progress in recent years, particularly in logic rewriting for the identification of potential subnetwork replacements. However, existing rewriting algorithms suffer from two major drawbacks: 1) inflexibility due to precomputed potential replacement candidates and 2) high-computational complexity of off-the-shelf conjunction normal form (CNF)-based SAT solvers. In this article, we propose a novel semi-tensor product (STP)-based exact synthesis approach for logic rewriting. The STP-based exact synthesis encodes Boolean functions into logic matrices and uses circuit-based all solutions SAT (AllSAT) solver to obtain all optimal replacement candidates with a single pass. Additionally, we improve the subnetwork selection strategy to allow flexible rewriting by selecting the most cost-effective implementation of all optimal candidates. Experimental results, compared with the state-of-the-art logic synthesis tool ABC, show that proposed STP-based exact synthesis reduces 41% runtime on average and solves all instances within a time limit. Moreover, after mapping into 6-LUT FPGA technology and standard cells, we obtain average improvements in the area of 6% and 18%, respectively.

A novel rectifier-less synchronous electric charge extraction and inversion (ReL-SECEI) interface circuit for Piezoelectric energy harvesters is proposed in this article. At the peak voltages of the Piezoelectric Transducer (PZT), a portion of electric charges is inverted on the clamped capacitance Cp, so that the PZT is automatically regulated at a higher output voltage state to improve extracted energy from the PZT. In addition, the self-powered implementation of the ReL-SECEI circuit is presented. It reduces the number of components by optimizing the positive and negative synchronous switches. The rectifier-less and simplified designs reduce the internal power loss and, hence, improve the energy harvesting efficiency. The ReL-SECEI circuit is verified by the experiment, the harvested power is load-dependent and the peak output power is obtained with the optimum load, which reaches 4.2 times that of the standard energy harvesting circuit.

A self-powered circuit for the combination of synchronized electric charge extraction (SECE) and synchronous magnetic flux extraction (SMFE) interfaces (SP-SECE-SMFE) is proposed, which can simultaneously extract energy from piezoelectric transducer (PZT) and electromagnetic transducer (EMT). It reveals that when the energy extraction time of PZT and EMT is consistent, the electromagnetic energy harvested by SP-SECE–SMFE is greatly improved due to the action of the pulse piezoelectric voltage and demonstrates how to use a resistance to adjust the energy extraction time of PZT. Simulation results show that the output power of SP-SECE–SMFE for the hybrid harvesting of piezoelectric and electromagnetic energy is 1.4–2.4 times higher than that of the sum when they are harvested separately under different frequencies and loads. The experimental results show that the maximum output power achieved by SP-SECE–SMFE is 1.7 times higher than that of the sum when are they harvested by the self-powered circuits of SECE and SMFE, respectively, and is 2.2 times higher than that of the half-bridge rectifier circuit. The simulation and experimental results show the superiority of the proposed SP-SECE–SMFE circuit.

Conventional multi-source energy harvesters use the time-division multiplexing (TDM) scheme, where the inductor operates in discontinuous current mode (DCM) and fails to perform well in continuous current mode (CCM). This article presents a single-inductor hybrid energy synchronous extraction circuit with serial stack resonance (SSR) for multi-source energy harvesting. The proposed circuit incorporates a synchronous electric charge extraction (SECE) circuit for ac energy and two buck–boost circuits for dc energy with a single inductor, which can operate either in a TDM mode to harvest energy from different sources separately or in an SSR mode to extract energy from multiple sources synchronously. The proposed harvester is fabricated in a 0.18- $\mu \text{m}$ CMOS process. It is configured with a photovoltaic (PV) cell, a thermoelectric generator (TEG), and two piezoelectric transducers (PZTs), where the number of PZTs is flexible to meet different application needs.

This letter presents a novel approach called energy harvesting and acceleration measuring (EHAM) using a single piezoelectric transducer (PZT). The energy-harvesting (EH) subsystem is a synchronous electric charge extraction (SECE) interface combining with an energy management circuit, which can harvest energy from PZT. The acceleration-measuring (AM) subsystem is for measuring acceleration-related signals. A time-division multiplexing strategy is employed in the EHAM system, where vibration energy is harvested during one period and vibration acceleration is measured in another period, and the harvested energy also powers the AM circuit. The prototyped EHAM system is implemented based on discrete components and tested with a conventional cantilever-based PZT harvester. Experimental results show that the EHAM system can perform EH and AM operations in a time-division multiplexing way. The EH circuit can harvest 1.76 mJ energy during 22 s with a PZT open-circuit voltage of 6 V. The AM circuit can measure accelerations with an accuracy of 95% under the mechanical resonance condition. The EHAM solution can be a candidate for self-powered acceleration measurement.

In the modern graphics processing unit (GPU)/artificial intelligence (AI) era, flip-flop (FF) has become one of the most power-hungry blocks in processors. To address this issue, a novel single-phase-clock dual-edge-triggering (DET) FF using a single-transistor-clocked (STC) buffer (STCB) is proposed. The STCB uses a single-clocked transistor in the data sampling path, which completely removes clock redundant transitions (RTs) and internal RTs that exist in other DET designs. Verified by post-layout simulations in 22 nm fully depleted silicon on insulator (FD-SOI) CMOS, when operating at 10% switching activity, the proposed STC-DET outperforms prior state-of-the-art low-power DET in power consumption by 14% and 9.5%, at 0.4 and 0.8 V, respectively. It also achieves the lowest power-delay-product (PDP) among the DETs.

Approximate computing (AC) offers benefits by reducing the requirement for full accuracy, thereby reducing power consumption and area. The majority logic (ML) gate functions as the fundamental logic block of many emerging nanotechnologies. In this article, ML-based arithmetic circuits, i.e., multibit adders and multipliers, are proposed. These adders are designed to prevent the propagation of inexact carry-out signals to higher order computing parts to enhance accuracy. We implemented the proposed multiplier by using a unique partial product reduction (PPR) circuitry, which was based on the parallel approximate 6:3 compressor. Several logic implementation costs, error metrics, and layouts implemented by quantum-dot cellular automata (QCA) are analyzed to evaluate the adder designs. A significant improvement is observed over previous ML-based designs based on the experimental results. The proposed designs are further evaluated using both a neural network (NN) accelerator and image processing. A structural similarity (SSIM) value of 1 and a peak signal-to-noise ratio (PSNR) value of infinity are achieved by the proposed adder design.

Driven by the explosive development of data-centric computation applications, it is becoming urgent to develop in-memory computing devices that are beyond the von Neumann architecture with an arrangement of separated logic and memory components. The transistor-type solid-state non-volatile memories, such as ferroelectric field-effect transistors (FeFETs), have long been regarded as a competitive candidate for future in-memory computing architectures. However, the density scaling towards high-density arrays would require advanced FeFETs with reduced footprints, which remains a great challenge so far. Here, a vertical-transport (VT) FeFET that flips the charge transport channel perpendicular to the substrate plane is proposed, in which a ferroelectric gate and a van der Waals (vdW) heterojunction channel are vertically integrated, effectively reducing the device footprints. The proposed VT-FeFET shows not only the robust binary non-volatile memory states but also several key synaptic functionalities at the device level. An artificial neural network with supervised learning was simulated based on the device conductance switching properties, showing excellent classification accuracy for the MNIST handwritten digits. These findings suggest that the proposed VT-FeFET could offer a new solution for future non-volatile memories as well as more advanced neuromorphic systems.

For ann-variable Boolean function, there are 2nfixed polarity Reed-Muller (FPRM) forms. In this paper, a frame of power dissipation, estimation for FPRM functions is presented and the polarity conversion is introduced to minimize the power for FPRM functions. Based on searching the best polarity for low power dissipation, an optimal algorithm is proposed and implemented in C. The algorithm is tested on seven single output functions from MCNC benchmark circuits. The experimental results are shown in this paper.