Search

On-chip non-volatile compute-in-memory (nvCIM) enables artificial intelligence (AI)-edge processors to perform multiply-and-accumulate (MAC) operations while enabling the non-volatile storage of weight data in power-off mode to enhance energy efficiency. However, the design challenges of nvCIM-based AI-edge processors include: 1) lack of a nvCIM-friendly computing flow; 2) a tradeoff between usage of memory devices versus process variations, computing yield and area overhead; 3) long computing latency and low energy efficiency; and 4) small-signal margin and large bitline current. This article presents an nvCIM-friendly AI-edge processor that uses a hybrid-mode resistive random access memory nvCIM (hmRe-nvCIM) macro to overcome the abovementioned challenges by three processor-level schemes: 1) a multimode nvCIM engine controller (mmCIM-EC); 2) a bitwise-input-sparsity and place-value-aware dynamic accumulation (BIS-PVA-DA); and 3) a bitwise weight column inversion (BWCI) and two macro-level schemes: 1) a dynamic-accumulation-aware current quantization (DACQ) and 2) a current–voltage-hybrid analog-to-digital converter (CVH-ADC). The proposed AI-edge processor fabricated using 22-nm technology achieved 51.4 TOPS/W and 472.7- $\mu \text{s}$ wake-up to response time, while the hmRe-nvCIM macro achieved 67.2 TOPS/W under 8-bit input, 8-bit weight, and 22- or 24-bit output precision.

Compute-in-memory (nvCIM) macros based on non-volatile memory make it possible for artificial intelligence (AI) edge devices to perform energy-efficient multiply-and-accumulate (MAC) operations by minimizing the movement of data between the processors and memory. However, nvCIM imposes tradeoffs between energy efficiency, computing latency, and readout accuracy against process variation. To overcome these challenges, this work proposed a nvCIM macro featuring: 1) a direct-current-free time-space-based in-memory computing (DCFTS-IMC) scheme; 2) a wordline-based serial access computing (WSAC) scheme; 3) an integration-based voltage-to-time converter (IVTC); and 4) a hidden-latency time-to-MAC value conversion (HLTMC) scheme. The proposed 22-nm 8-Mb resistive random access memory-CIM (ReRAM-CIM) macro was fabricated to demonstrate MAC operations with 8-b input, 8-b weight, and 19-b output. Our nvCIM macro achieved computing latency of 14.4 ns under 8-b precision with an energy efficiency of 21.6 TOPS/W.