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Advanced CMOS Scaling has benefited from the introduction of novel materials and integration techniques over the past two decades. Consumer demand for more connectivity and real-time information continues to drive the need for product solutions with advanced power management and increased functionality while maintaining low cost. New device architectures such as FINFET and Fully Depleted Silicon-On-Insulator are part of the solution, however these device architectures still rely on advanced channel strain engineering to meet power, performance, and scaling requirements. The use of SiGe as a channel material is attractive due to enhanced mobility and compatibility with standard CMOS processing. PFET drive current enhancement has already been realized to enable platforms based on high performance planar FDSOI devices, while SiGe as part of the channel is also a top solution to enable next generation FINFET and Gate-All-Around devices. In this invited paper we will provide a look into the device benefits and challenges of SiGe as a channel material.

A novel fluorescence spectrometer and method for the simultaneous detection of multiple-fluorophore species in a no-moving-parts, instantaneous manner is described. In the reported embodiment of the instrument, a tapered Fabry–Perot filter is used to spatially encode the fluorescence spectrum from a multiple-dye-containing test sample. Using a pseudoinverse reconstruction algorithm, we spectrally decode the particle concentration for each dye specie in the test sample. Experimental results are reported along with a theoretical treatment of the method.

Advanced CMOS Scaling has benefited from the introduction of novel materials and integration techniques over the past two decades. Consumer demand for more connectivity and real-time information continues to drive the need for product solutions with advanced power management and increased functionality while maintaining low cost. New device architectures such as FINFET and Fully Depleted Silicon-On-Insulator are part of the solution, however these device architectures still rely on advanced channel strain engineering to meet power, performance, and scaling requirements. The use of SiGe as a channel material is attractive due to enhanced mobility and compatibility with standard CMOS processing. PFET drive current enhancement has already been realized to enable platforms based on high performance planar FDSOI devices, while SiGe as part of the channel is also a top solution to enable next generation FINFET and Gate-All-Around devices. In this invited paper we will provide a look into the device benefits and challenges of SiGe as a channel material.

After decades of research, high-k metal gate has been successfully integrated into CMOS starting with the 45nm node. To continue scaling, the industry has chosen two integration approaches: FINFET with gate last and FDSOI with gate first. The FINFET with gate last integration was introduced into production at the 22nm node by Intel. The FDSOI with gate first integration was introduced into production at 28nm node by ST Microelectronics. There are some common factors impacting threshold voltage (Vt) on both integrations such as the high-k/metal gate film thickness and composition as well as the doping concentration. Beyond that, each integration approach has its own unique challenges that must be overcome to achieve targeted Vt and maintain Vt control. In this work we will highlight those unique challenges and discuss what knobs can be used to achieve the targeted Vt and maintain Vt control.