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This study relates to the selective area growth (SAG) of III-V semiconductors on Silicon substrates. Both approaches, growth in trenches and NWs bottom-up growth, are considered and discussed. We demonstrated in a first part a high control of the two-step InP buffer growth in STI trench width below 20 nm. First GaAs NWs from production MOVPE tool are also shown in a second part. Finally we conclude with the different applications using III-V semiconductors successfully integrated on Silicon substrates.

The impact of the well doping profile on the current–voltage (I-V) and capacitance–voltage (C-V) characteristics of cobalt-silicided n+-pp+-n junction diodes fabricated in a 0.18 βm CMOS compatible processing scheme is studied. It will be shown that the nature of the junction (abrupt or linearly graded) has a strong influence on the resulting leakage current. Moreover, the extra thermal budget to create a nitrided gate oxide may drastically change the B-profile in the p-well and deteriorate the overall characteristics. From a detailed analysis, it is concluded that the increased leakage current observed for the nitrided case occurs at the perimeter of the diodes, where the Co-silicide may form a Schottky contact with the underlying n- or p-well. In order to control the leakage, the overall thermal budget should be optimized, particularly with respect to the back-end processing.

The impact of different isolation schemes on the p–n junction characteristics is compared. From the diode current–voltage behaviour, the silicon generation and recombination lifetime is extracted. It will be shown that the recombination lifetime is higher in the case of shallow trench isolation (STI) than in the case of polysilicon encapsulated local oxidation of silicon (PELOX). The opposite trend is observed for the generation lifetime. These results will be discussed in view of the defects present in the p-well of the diodes, which are studied by other spectroscopic and microscopic techniques.

Shallow trench isolation (STI) is a promising technology for the isolation structures of the new generation of ULSI devices with dimensions below 0.18μm. The various processing steps cause stress fields in STI structures, which can lead to defect formation in the silicon substrate. In their turn, stress fields affect the electrical parameters and the reliability of devices. Convergent beam electron diffraction (CBED) is used in this study to examine the influence of a wet and a dry pre-gate oxidation on the stress distribution around STI structures. The measurements are performed on STI structures with different width and spacing. CBED analysis is compared with bright-field TEM images. Defects are observed in high-strain areas of small isolated structures.

This study relates to the selective area growth (SAG) of III-V semiconductors on Silicon substrates. Both approaches, growth in trenches and NWs bottom-up growth, are considered and discussed. We demonstrated in a first part a high control of the two-step InP buffer growth in STI trench width below 20 nm. First GaAs NWs from production MOVPE tool are also shown in a second part. Finally we conclude with the different applications using III-V semiconductors successfully integrated on Silicon substrates.

This work presents a study of the temperature impact on the performance of nanowire tunnel field effect transistors (TFETs). After explaining the fundamental working principles based on simulated energy band diagrams, experimental data were analyzed for temperatures ranging from 300 to 420 K. Therefore, it was possible to evaluate the TFET performance regarding the subthreshold slope (S) and the on-state and off-state current ratio (ION/IOFF) for different nanowire diameters and bias conditions. The drain current susceptibility to the temperature can be explained based on the influence of each of the most relevant transport mechanisms (band-to-band tunneling, trap-assisted tunneling and Shockley-Read-Hall generation/recombination). The resulting subthreshold slopes in the different regions were compared to the 60 mV/dec limit at room temperature for standard MOSFET devices. It was observed that the ION/IOFFratio increased for larger nanowire diameters but decreased for higher temperatures. Drain current was reported to be much less influenced by the temperature for higher gate voltage values, when band-to-band tunneling prevailed over the other components.

This work presents the analog performance of nMOS and pMOS triple-gate FinFETs with high-k dielectrics, TiN gate material and undoped body from DC measurements. Different fin widths and devices with and without halo implantation are explored. No halo FinFETs can achieve extremely large gain at similar channel length and improved unity gain frequency. The FinFETs with channel length of 110 nm achieved an intrinsic gain of 25 dB. Extremely large Early voltages have been measured on long channel nMOS and pMOS with relatively wide fins compared to the results usually reported in the literature. The large Early voltage obtained suggests the devices are in the onset of volume inversion phenomena due to the low doping level of the device body.

This paper studies the temperature reduction influence on some analog figures of merit of n-type triple-gate FinFETs with undoped body, using DC measurements. It is demonstrated that the temperature reduction improves the transconductance over drain current ratio in any operational region. On the other hand, the output conductance is degraded when the temperature is reduced. The combination of these effects shows that the intrinsic gain of a L=90 nm FinFET is degraded by 3 dB when the temperature reduces from 300 K down to 100 K. A comparison with planar single gate fully depleted SOI reveals that the temperature degradation of the output conductance in FinFETs is less temperature-dependent.