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Flying capacitor multilevel (FCML) converters typically rely on natural balancing to achieve a balanced distribution of flying capacitor voltages. The mechanisms by which the flying capacitor voltages are able to balance have been extensively studied and theoretically there are certain combinations of level count and duty cycle at which the flying capacitor voltages do not balance. Although the flying capacitor voltages should diverge from the balanced distribution, in practice this behavior is rarely observed. To resolve this discrepancy between FCML converter theory and experiment, this article analyzes the impact of switch output capacitance on the flying capacitor voltage balancing dynamics, and illustrates that this capacitance has a naturally balancing effect. The additional mechanism of switch output capacitance induced balancing is analytically described and compared against experimental results on several FCML converter prototypes.

This work presents a capacitor voltage balancing controller for current-controlled flying capacitor multilevel converters. A small-signal model of the converter derived from state–space averaging informs the parallel controller structure. The proposed controller incorporates nonlinear actions to decouple flying capacitor control loops and prevent adverse interaction between the capacitor voltage balancing and inductor current controllers. Experimental results of closed-loop line and load transient responses demonstrate significant performance improvements with the proposed balancing architecture compared to a converter relying on natural capacitor balancing. These improvements are quantified with experimental measurements of switch voltage stress and load current disturbance as a response to line voltage perturbations at different frequencies. Limits to control bandwidths in balancing controllers based on averaged models are discussed. The closed-loop stability of the converter operating with the proposed active balancing architecture is discussed as a function of the operating point, controller gains, and hardware parameters, such as output filter inductance and inductor current ripple.

This article proposes an ultra-high-current 48-V-to-1-V hybrid switched-capacitor (SC) voltage regulator, named the switching bus converter, with a single-stage vertical power delivery architecture for next-generation ultra-high-power processors (e.g., graphics processing units, central processing units, application-specific integrated circuits, etc.). The proposed topology consists of two 2-to-1 SC front-ends and four 10-branch series-capacitor-buck modules, merged through four switching buses. Compared to the existing dc-bus-based architecture, the proposed switching-bus-based architecture eliminates the need for dc bus capacitors, reduces the switch count, and guarantees complete soft-charging operation. Through a topological comparison, this article reveals that the proposed topology achieves the lowest normalized switch stress and the smallest normalized passive component volume among existing 48-V-to-1-V hybrid SC demonstrations, showing great potential for both higher efficiency and higher power density than prior hybrid SC solutions. A hardware prototype was designed and built with custom four-phase coupled inductors and gate drive daughterboards to validate the functionality and performance of the proposed switching bus converter. It was tested up to 1500-A output current and achieved 92.7% peak system efficiency, 85.7% full-load system efficiency (including gate drive loss), and 759 W/in$^{3}$ power density (by box volume), pushing the performance limit of the state-of-the-art 48-V-to-1-V solutions toward higher efficiency and higher power density.

Dielectric electrostatic capacitors1, because of their ultrafast charge–discharge, are desirable for high-power energy storage applications. Along with ultrafast operation, on-chip integration can enable miniaturized energy storage devices for emerging autonomous microelectronics and microsystems2–5. Moreover, state-of-the-art miniaturized electrochemical energy storage systems—microsupercapacitors and microbatteries—currently face safety, packaging, materials and microfabrication challenges preventing on-chip technological readiness2,3,6, leaving an opportunity for electrostatic microcapacitors. Here we report record-high electrostatic energy storage density (ESD) and power density, to our knowledge, in HfO2–ZrO2-based thin film microcapacitors integrated into silicon, through a three-pronged approach. First, to increase intrinsic energy storage, atomic-layer-deposited antiferroelectric HfO2–ZrO2films are engineered near a field-driven ferroelectric phase transition to exhibit amplified charge storage by the negative capacitance effect7–12, which enhances volumetric ESD beyond the best-known back-end-of-the-line-compatible dielectrics (115 J cm−3) (ref. 13). Second, to increase total energy storage, antiferroelectric superlattice engineering14scales the energy storage performance beyond the conventional thickness limitations of HfO2–ZrO2-based (anti)ferroelectricity15(100-nm regime). Third, to increase the storage per footprint, the superlattices are conformally integrated into three-dimensional capacitors, which boosts the areal ESD nine times and the areal power density 170 times that of the best-known electrostatic capacitors: 80 mJ cm−2and 300 kW cm−2, respectively. This simultaneous demonstration of ultrahigh energy density and power density overcomes the traditional capacity–speed trade-off across the electrostatic–electrochemical energy storage hierarchy1,16. Furthermore, the integration of ultrahigh-density and ultrafast-charging thin films within a back-end-of-the-line-compatible process enables monolithic integration of on-chip microcapacitors5, which can unlock substantial energy storage and power delivery performance for electronic microsystems17–19.

The conventional dc-link aluminum electrolytic capacitor bank simply, efficiently, and cost-effectively decouples the instantaneous power mismatch inherent to all single-phase ac–dc power converters. However, the practical realization of the capacitor bank remains largely qualitative and dependent on the opaque performance capabilities of the capacitor technology. This work presents an exhaustive survey of commercial aluminum electrolytic capacitors and defines both quantitative and justly comparative device-level figures-of-merit (FOM). By configuring the relative voltage ripple ratio specification $\alpha$ of the dc bus, these device FOM enable the determination of minimal dc-link capacitor volume, cost, and/or mass. Graphical illustration demonstrates that the set of commercially available yet viable components diminishes as specification $\alpha$ increases; the realized dc-link capacitor bank volume and cost will grow appreciably for ${\alpha >\!10\,{\%}}$ and ${\alpha >\!5\,{\%}}$, respectively.

The wide integration of inverter based renewable energy sources (RESs) in modern grids may cause severe voltage violation issues due to high stochastic fluctuations of RESs. Existing centralized approaches can achieve optimal results for voltage regulation, but they have high communication burdens; existing decentralized methods only require local information, but they cannot achieve optimal results. Deep reinforcement learning (DRL) based methods are effective to deal with uncertainties, but it is difficult to guarantee secure constraints in existing DRL training. To address the above challenges, this paper proposes a projection embedded multi-agent DRL algorithm to achieve decentralized optimal control of distribution grids with guaranteed 100% safety. The safety of the DRL training is guaranteed via an embedded safe policy projection, which could smoothly and effectively restrict the DRL agent action space, and avoid any violation of physical constraints in distribution grid operations. The multi-agent implementation of the proposed algorithm enables the optimal solution achieved in a decentralized manner that does not require real-time communication for practical deployment. The proposed method is tested in modified IEEE 33-bus distribution and compared with existing methods; the results validate the effectiveness of the proposed method in achieving decentralized optimal control with guaranteed 100% safety and without the requirement of real-time communications.

This article proposes a switching bus converter, an efficient and compact hybrid switched-capacitor (SC) voltage regulator, for direct 48 V to point-of-load power conversion in data centers. The proposed topology merges a 2-to-1 SC front-end with two eight-branch series-capacitor-buck (SCB) modules through two switching buses. Compared with the existing dc-bus-based architecture, the proposed switching-bus-based architecture does not require dc-bus capacitors, reduces the number of switches, and ensures complete soft-charging operation. In addition, this article conducts a comparative performance analysis of different regulated hybrid SC topologies, which reveals that a larger SC conversion ratio is advantageous for achieving higher performance. Through the two-phase operation of the SCB modules, the proposed topology extends the maximum duty ratio and enables a larger SC conversion ratio. A hardware prototype was designed and built with custom two-phase coupled inductors and synchronous bootstrap daughterboards to validate the theoretical potential of the proposed topology. The hardware prototype was tested up to 500-A output current at 1-V output voltage, achieving 93.4% peak system efficiency, 86.1% full-load system efficiency, and 464-W/in$^{3}$ power density. Moreover, the theoretical benefits of a larger SC conversion ratio were experimentally verified with measured performance at different SC conversion ratios.

This article presents a general analytical framework enabling the large-signal characterization of resonant switched-capacitor (ReSC) power converters that accounts for passive component voltage and current ripple, for operation at and above resonance. From this, appropriate phase durations for minimized rms currents are derived, in addition to expressions for total passive component volume using an intuitive peak energy method. An example hardware prototype validates both the derived waveforms and timings—as well as total passive volume—through three comparable hardware configurations, one of which minimizes passive component volume. In addition, the proposed technique formulates analytical expressions for both rms currents and peak blocking voltages, facilitating refined loss estimation and component selection. Subsequent calculation of the large-signal volt-amp switch stress metric allows a more accurately quantified tradeoff between active and passive components compared to prior work, which has not fully accounted for ripple. Four common ReSC topologies are exemplified throughout, with topology-specific parameters documented for reference.

In pre-existing analytical models of switched-capacitor (SC) converters, the input and output capacitances ($C_{\text{in}}$ and $C_{\text{out}}$) have long been assumed to be infinitely large so that the input and output can be modeled as ideal voltage sources. However, in practice, the terminal capacitances can be insufficient to ensure ideal input and output behaviors due to space and cost constraints. This article reveals that finite terminal capacitances can have considerable effects on the output impedance ($R_{\text{out}}$) and overall efficiency of SC converters. A general modeling and analysis methodology is proposed for SC converters to characterize the effects of finite terminal capacitances quantitatively. A 2-to-1 SC converter prototype is specially designed to verify the proposed general output impedance model. The relative error between the modeling results and the experimental measurements is less than 8%, which demonstrates the excellent accuracy of the proposed model. It is revealed that the insufficiency in $C_{\text{in}}$ can lead to a considerably higher $R_{\text{out}}$ and harm the overall efficiency. On the contrary, decreasing $C_{\text{out}}$ can counter-intuitively help reduce $R_{\text{out}}$, which contributes to both higher efficiency and higher power density, although this benefit comes at the cost of a larger output voltage ripple. In addition, $C_{\text{out}}$ has a stronger effect on $R_{\text{out}}$ in the slow switching region, while $C_{\text{in}}$ is more influential in the fast switching region, especially around the knee of the output impedance curve, which is the typical operating point of SC converters. Several design guidelines are provided based on these findings. Further discussions are provided to explain how to apply the proposed general output impedance model to arbitrary SC topologies.

This work introduces the symmetric dual inductor hybrid (SDIH) dc–dc converter topology, which is suitable for large conversion ratios where regulation is required, such as direct 48 V to point-of-load (PoL) applications. A Dickson-type switched capacitor network is used to effectively produce two interleaved pulsewidth-modulated (PWM) outputs with a greatly reduced voltage amplitude relative to the input voltage, allowing the subsequent magnetic volume to be reduced while retaining modest switching frequencies. Distinct from related variations, part count is significantly reduced while both even and odd order switched capacitor networks can be used with straightforward split-phase control; allowing either network type to achieve complete soft-charging of all flying capacitors. Additionally, charge flow is uniformly distributed through all elements, with equal capacitor and inductor values being preferred. Subsequently, this topology is expected to simplify component selection, improve electrical and thermal performance, and reduce cost. Furthermore, analysis is presented that calculates precise phase durations without making small ripple assumptions, revealing up to a 75% timing error in cases where either inductor or capacitor ripple is ignored. Finally, a discrete prototype validates this analysis and demonstrates very high measured power densities of 1029, 754, and 663 W/in$^{3}$ for 48 V input and regulated output voltages of 3, 2, and 1 V, respectively, while switching at a frequency of 750 kHz.

To realize high efficiency and high power density for resonant switched-capacitor (ReSC) converters, it is critical to have a thorough understanding of the soft-switching mechanism and design the converter appropriately. However, this can be challenging as the soft-switching operation depends on multiple variables and its design difficulty increases quickly with respect to the topology complexity. This article demonstrates a framework for using geometrical state-plane analysis to facilitate ReSC converter design. The methodology is first applied to a basic 2-to-1 ReSC converter and then extended to a new 4-to-1 ReSC converter topology we proposed, herein named a cascaded multiresonant converter. This topology has a reduced component count thanks to a new “switching bus” architecture. However, it comes at a cost, as the converter has multiple resonances within each switching cycle, complicating the soft-switching design. Despite the high circuit complexity, the state-plane analysis neatly provides analytical equations for all state parameters, which are verified by simulations and experiments. Our hardware prototype achieves 6000 W/in3 power density at 48-to-12 V conversion and 80 A continuous output. Its peak efficiency reaches 99.02%, and full-load efficiency reaches 97.67%, including gate drive loss. Both the power density and efficiency are superior to the state-of-the-art 48-to-12 V solutions.

Designing and optimizing high switching frequency, ultra-efficient converters requires detailed knowledge of the behavior and parasitic parameters for both active and passive components. Recently, wide bandgap transistors have enabled simultaneous increases in both switching frequency and efficiency due to higher maximum operating junction temperature limits, lower dc on-state resistances, and reduced parasitic inductances and capacitances. Yet, the early acceptance of gallium-nitride (GaN) switches was plagued by detrimental dynamic on-state resistance effects. This complex phenomenon for GaN devices is characterized by deviations in on-state resistance from dc operating characteristics based on design choices such as the magnitude and duration of both voltage and current stress, switching mode, and junction temperature. While device manufacturers have made improvements compared to early generation devices, experimental evidence from a survey of commercial GaN transistors highlight measurable change in on-state resistance still exists due to variations in voltage stress during hard-switching operation. After sharing insights for obtaining low noise measurements, an analysis method along with two metrics are proposed to characterize dynamic on-state resistance measurements for power electronics designers. Quantifying the performance of GaN devices with standardized metrics facilitates a fair comparison between different GaN device technologies during converter development, enables manufacturing qualification for GaN switches, and provides a benchmark to catalyze improvement for the next generation of GaN device development.

Switched capacitor converters (SCCs) have been widely investigated and used in both academia and industry for many years, ranging from low power (milliwatt level) to high power (several kilowatt levels) for a myriad of applications. SCCs offer several advantages, including the elimination of inductor and related magnetic design issues and hence low electromagnetic interference (EMI), better form factor or power density, and improved dynamic response. Despite tremendous benefits, the main drawback of SCCs is their inevitable inrush current during capacitors' charging or charge sharing process by their parallel connection with the dc-link adversely impacting the stress on the power devices and thus reducing the efficiency and reliability of the system. However, there is still a huge room for performance improvement in SCCs by introducing a small resonant inductor or by integrating the best features of capacitive and inductive power conversion. Such a “hybrid” concept can simultaneously achieve high efficiency, reliability, and power density.

The series-stacked architecture provides a method to increase power delivery efficiency to multiple processors by leveraging the inherent voltage step-down properties of series-connected elements. With a series stack, differential power processing (DPP) is needed to ensure that processor voltages remain within design limits, as the individual loads vary. This paper demonstrates a switched-capacitor (SC) converter to balance a stack of four ARM Cortex-A8-based embedded computers. We investigate hard-switched and resonant modes of operation in a ladder SC DPP converter implemented with GaN transistors. Operation within supply limits of each embedded computer is demonstrated in a four-series-stack configuration with realistic computational workloads. Moreover, we demonstrate hot-swapping of individual computers with maintained voltage regulation at all nodes. A peak stack power delivery of 99% is experimentally measured, and DPP switching frequencies from 200 kHz to 2 MHz are demonstrated.

Multilevel topologies are an appealing method to achieve higher power density converters for both mobile and stationary systems. This article discusses the design and high-performance hardware implementation of a 13-level, flying capacitor multilevel (FCML) inverter. Derivation of flying capacitor sizing for ac output voltages (for an arbitrary level FCML) is provided. Operating from an 800-Vdc bus, this hardware prototype utilizes switch modules with 100-V rating. Moreover, a 120-kHz switching frequency is enabled through the use of gallium nitride (GaN) FETs and the development of custom-integrated switching cells, which reduce commutation loop inductance and allow for a modular design. The frequency multiplication effect of FCML inverters allows the output inductor of the inverter to be made exceptionally small (4.7 μH) while maintaining a 0.7% total harmonic distortion (THD) due to the 1.44-MHz effective inductor ripple frequency.

The series-stacked buffer (SSB) is an active twice-line frequency energy decoupling buffer architecture in single-phase converters. The high power density and efficiency characteristics of this architecture have been recently demonstrated. However, in previous hardware work on the SSB, the energy utilization ratios of the buffer capacitors are not optimized, and the tradeoff among loss, volume, and bus voltage ripple has not been quantitatively studied. In this article, we propose a methodology that quantifies and formalizes the SSB design process into a multiobjective optimization problem, from which the loss-volume Pareto front can be solved, and an optimal control strategy for minimum loss can be determined. Design constraints, modeling of objective functions, and optimization algorithms are discussed. With realistic hardware parameters and constraints, this methodology is applied to the SSB design for a 1.5-kW, 400-V dc-bus single-phase system. The corresponding Pareto front results are studied with hardware prototypes. Compared with previous SSB hardware demonstrations, both power density and efficiency of the designed hardwares are substantially enhanced with the proposed method.

Switched capacitor converters (SCCs) have been widely investigated and used in both academia and industry for many years, ranging from low power (milliwatt level) to high power (several kilowatt levels) for a myriad of applications. SCCs offer several advantages, including the elimination of inductor and related magnetic design issues and hence low electromagnetic interference (EMI), better form factor or power density, and improved dynamic response. Despite tremendous benefits, the main drawback of SCCs is their inevitable inrush current during capacitors' charging or charge sharing process by their parallel connection with the dc-link adversely impacting the stress on the power devices and thus reducing the efficiency and reliability of the system. However, there is still a huge room for performance improvement in SCCs by introducing a small resonant inductor or by integrating the best features of capacitive and inductive power conversion. Such a “hybrid” concept can simultaneously achieve high efficiency, reliability, and power density.

Switched capacitor converters (SCCs) have been widely investigated and used in both academia and industry for many years, ranging from low power (milliwatt level) to high power (several kilowatt levels) for a myriad of applications. SCCs offer several advantages, including the elimination of inductor and related magnetic design issues and hence low electromagnetic interference (EMI), better form factor or power density, and improved dynamic response. Despite tremendous benefits, the main drawback of SCCs is their inevitable inrush current during capacitors’ charging or charge sharing process by their parallel connection with the dc-link adversely impacting the stress on the power devices and thus reducing the efficiency and reliability of the system. However, there is still a huge room for performance improvement in SCCs by introducing a small resonant inductor or by integrating the best features of capacitive and inductive power conversion. Such a “hybrid” concept can simultaneously achieve high efficiency, reliability, and power density.

This paper presents a power factor correction (PFC) front end based on a seven-level flying capacitor multilevel (FCML) boost converter. Compared to the conventional two-level boost converter, the proposed seven-level FCML converter features the use of low-voltage-rated transistors, reduced voltage stress, and high effective switching frequency on the filter inductor. These characteristics of the FCML converter lead to drastic reduction in the filter inductor size while maintaining high efficiency and, therefore, significantly improve the power density of the PFC front end compared to conventional solutions. On the other hand, the small inductance imposes challenges on the PFC control. The dynamics of the seven-level FCML converter has been analyzed, and a feedforward control has been implemented to overcome these challenges. A hardware prototype is designed for universal ac input (90 to 265 Vac), 400-V dc output, and 1.5-kW power rating. Compared to existing solutions, the hardware prototype demonstrates improved efficiency and power density while maintaining high power factor and low THD. A power density of 219 W/in3 (490 W/in3 for the power stage) has been achieved, and a peak efficiency of 99.07% has been experimentally verified.

This paper presents an integrated maximum power point tracking system for use with a thermophotovoltaic portable power generator. The design, implemented in 0.35-μm CMOS technology, consists of a low-power control stage and a dc-dc boost power stage with soft-switching capability. With a nominal input voltage of 1 V, and an output voltage of 4 V, we demonstrate a peak conversion efficiency under nominal conditions of over 94% (overall peak efficiency over 95%), at a power level of 300 mW. The control stage uses lossless current sensing together with a custom low-power time-based analog-to-digital converter to minimize control losses. The converter employs a fully integrated digital implementation of a peak power-tracking algorithm, and achieves a measured tracking efficiency above 98%. A detailed study of achievable efficiency versus inductor size is also presented, with the calculated and measured results.

This paper describes a distributed maximum power point tracking control scheme for photovoltaic (PV) systems at the submodule level. The system employs isolated differential power processing (DPP) converters that require no perturb and observe synchronization and little communication among power converters themselves. Design and benefits of this architecture with respect to control, communication, and converter efficiency are analyzed. Isolated dc-dc converter prototypes are constructed and employed within a string of series-connected PV submodules to experimentally validate the proposed control method. An experimental extraction efficiency of 99.12% is achieved for a three submodule connection with ~30% mismatch-a 10.19% improvement from the conventional, non-DPP architecture.

Power electronics are vital for the generation, conversion, transmission, and distribution of electrical energy. Improving the efficiency, power density, and reliability of power electronics is an important challenge that can be addressed with electrothermal codesign and optimization. Current thermal management approaches utilize metallic heat sinks (HSs), resulting in parasitic load generation due to different potentials between electronic components on the printed circuit board (PCB). To enable electrical isolation, a thermal interface material (TIM) or gap pad is placed between the PCB and HS, resulting in poor heat transfer. Here, we develop an approach to eliminate TIMs and gap pads through modularization of metallic HSs. The use of smaller modular heat sinks (MHSs) strategically placed on high power dissipation areas of the PCB enables elimination of electrical potential difference, and removal of electrical isolation materials, resulting in better cooling performance due to direct contact between devices and the HS. By studying a gallium nitride (GaN) 2 kW DC–DC power converter as a test platform for electrothermal codesign using the modular approach, and benchmarking performance with a commercial off-the-shelf HS design, we showed identical power dissipation rates with a 54% reduction in HS volume and a 8 °C reduction in maximum GaN device temperature. In addition to thermal performance improvement, the MHS design showed a 73% increase in specific power density with a 22% increase in volumetric power density.