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In this paper, we present an innovative approach to reduce power and accelerate timing closure by using simulated silicon-calibrated contours to predict the litho effects on transistor gates and perform litho-aware critical paths analysis. This approach is used to filter the false hold time violations and focus designers' actions on the most relevant violations. After silicon validation, the application of this technique to hold time fixing on a 90nm micro-controller unit product reduces the power increase and runtime of the hold buffer insertion. This study not only demonstrates the feasibility of the Litho-aware STA flow but also shows its value to reduce hold time fixing effort and power dissipation caused by buffer insertion.

The luminescent properties of porous silicon (PS) have been studied in terms of its electrical properties and photo-conduction effects. It is shown that the electrical conduction mode of the PS layers at low temperatures below about 100 K is dominated by tunneling either in the dark or under illumination, and that the photoconduction spectra of efficiently luminescent PS almost coincide with the photoluminescence (PL) excitation spectra. The implication is that the electronic excitation for both photoconduction (PC) and PL occurs in the same place. Effects of electric field on the PL characteristics of PS are also studied in relation to PC effects. The experimental data demonstrate that the degree of electric-field PL quenching corresponds to the net PC current induced during PL excitation. These observations are discussed in relation to the visible luminescence mechanism.