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This paper aims to present an overview of the existing wafer-to-wafer alignment technology. The development of optical alignment methods will be reviewed with respect to applications requirements evolution over time. An overview of the different factors contributing to the overall misalignment budget and how they are controlled now, or will be in the future, in order to meet the stringent requirements will be presented with examples.

Backside illuminated image sensors combine small pixel area with high signal-to-noise ratio. Wafer bonding is a key enabling process step for manufacturing of backside illuminated image sensors. The fully CMOS processed image sensor wafer is bonded to a blank silicon carrier wafer and then back thinned to reveal the photodiodes. As a result the photodiodes are on top of the metal interconnects thereby eliminating any shading of the photosensitive area. Plasma activated fusion wafer bonding enables a room temperature wafer bonding with highest wafer-to-wafer alignment accuracy.

The ITRS roadmap for high-density TSV interconnects specifies maximum layer thicknesses of 5-15 um in 2013 with a sub-micron layer-to-layer alignment accuracy. For 3D chip stacks with multiple layers it is not only necessary to handle and process such thin layers, but later on these thin layers have to be stacked and bonded. When it comes to wafer bonding for high-density TSV integration, most efforts have been given to developing Cu-Cu thermo-compression bonding and direct oxide bonding. Stacking of thin wafers can be performed either after the thin wafer is debonded or while the thin wafer is still bonded onto a carrier wafer. Bonding of the thin wafer while still mounted to the carrier wafer allows comfortable and safe wafer handling, but adds some complexity to the wafer bonding process.

Recently adhesive wafer bonding using SU-8 has gained a lot of interest for micro-fluidic devices e.g. lab-on-chip applications. Due to its specific properties as well as the capability to pattern thin and thick layers accurately, SU-8 is an ideal candidate for micro-fluidic components like channels, reservoirs and valves, but also for micro-optical components. Wafer bonding enables the capping and encapsulation of the devices. In this paper the state-of-the-art of SU-8 wafer bonding is presented with a higher emphasis on the impact of the pre- processing. Spin-, spray coating and dry film lamination are reviewed and the resulting bond properties are analyzed.

Plasma activated wafer bonding generated a high interest in last decade due to the important process temperature reduction. With the main advantage of bringing some applications at industrial degree of feasibility. An example of process which benefits from this new process is silicon fusion bonding: by using plasma activation the bond process temperature and time are reduced at values which make wafer bonding compatible with industrial manufacturing requirements. A newly developed process allowing bonding of two substrates in the plasma activation chamber is foreseen as a very interesting approach for numerous applications, especially in the field of engineered substrates fabrication.

AbstractWe describe a versatile infrared camera/spectrograph, IRIS, designed and constructed at the Anglo-Australian Observatory for use on the Anglo-Australian Telescope. A variety of optical configurations can be selected under remote control to provide several direct image scales and a few low-resolution spectroscopic formats. Two cross-dispersed transmission echelles are of novel design, as is the use of a modified Bowen-Burch system to provide a fast f/ratio in the widest-field option. The drive electronics includes a choice of readout schemes for versatility, and continuous display when the array is not taking data, to facilitate field acquisition and focusing.The linearity of the detector has been studied in detail. Although outwardly good, slight nonlinearities prevent removal of fixed-pattern noise from the data without application of a cubic linearising function.Specific control and data-reduction software has been written. We describe also a scanning mode developed for spectroscopic imaging.

This article presents executives' economic outlook for the business world, particularly the semiconductor industry, in 2009. Ardy Johnson, vice president of marketing at Rudolph Technologies Inc., stated that well-managed growth and successful acquisitions will become a valuable competitive advantage for semiconductor firms. Ludo Deferm, executive vice president of IMEC, said that companies will continue to seek new markets.

Focuses on wafer-level 3-D integration using aligned wafer bonding. 3-D integration comparison; Key processing challenges for a back-end compatible wafer-level 3-D platform; Major approaches for wafer bonding for wafer-level 3-D integration.

This paper aims to present an overview of the existing wafer-to-wafer alignment technology. The development of optical alignment methods will be reviewed with respect to applications requirements evolution over time. An overview of the different factors contributing to the overall misalignment budget and how they are controlled now, or will be in the future, in order to meet the stringent requirements will be presented with examples.

Backside illuminated image sensors combine small pixel area with high signal-to-noise ratio. Wafer bonding is a key enabling process step for manufacturing of backside illuminated image sensors. The fully CMOS processed image sensor wafer is bonded to a blank silicon carrier wafer and then back thinned to reveal the photodiodes. As a result the photodiodes are on top of the metal interconnects thereby eliminating any shading of the photosensitive area. Plasma activated fusion wafer bonding enables a room temperature wafer bonding with highest wafer-to-wafer alignment accuracy.

The ITRS roadmap for high-density TSV interconnects specifies maximum layer thicknesses of 5-15 µm in 2013 with a sub-micron layer-to-layer alignment accuracy. For 3D chip stacks with multiple layers it is not only necessary to handle and process such thin layers, but later on these thin layers have to be stacked and bonded. When it comes to wafer bonding for high-density TSV integration, most efforts have been given to developing Cu-Cu thermo-compression bonding and direct oxide bonding. Stacking of thin wafers can be performed either after the thin wafer is debonded or while the thin wafer is still bonded onto a carrier wafer. Bonding of the thin wafer while still mounted to the carrier wafer allows comfortable and safe wafer handling, but adds some complexity to the wafer bonding process.

Wafer bonding became a powerful industrial technology for various applications in the fields of Micro- Electro-Mechanical Systems (MEMS), wafers stacking for 3D interconnects, wafer level packaging and other areas where new materials combinations are facilitated by the use of different bonding processes. An important enlargement of wafer bonding applications field was brought by new developments in the area of low temperature wafer bonding processes (maximum temperature of 400{degree sign}C): with such processes wafer bonding can be applied for fully patterned wafers (e.g. CMOS), IC wafers (e.g. for 3D interconnects) or silicon direct bonding can now be performed in standard industrial wafer bonding equipment. Plasma activated wafer bonding is a process in which the two substrates are submitted to a plasma treatment prior to bringing them into contact. This surface treatment allows the control of surface chemistry and results in obtaining a high bond strength at low annealing temperatures and short thermal annealing times. This paper reports new results obtained for different applications using plasma activated wafer bonding.

Recently adhesive wafer bonding using SU-8 has gained a lot of interest for micro-fluidic devices e.g. lab-on-chip applications. Due to its specific properties as well as the capability to pattern thin and thick layers accurately, SU-8 is an ideal candidate for micro-fluidic components like channels, reservoirs and valves, but also for micro-optical components. Wafer bonding enables the capping and encapsulation of the devices. In this paper the state-of-the-art of SU-8 wafer bonding is presented with a higher emphasis on the impact of the pre- processing. Spin-, spray coating and dry film lamination are reviewed and the resulting bond properties are analyzed.

Wafer bonding became a powerful industrial technology for various applications in the fields of Micro- Electro-Mechanical Systems (MEMS), wafers stacking for 3D interconnects, wafer level packaging and other areas where new materials combinations are facilitated by the use of different bonding processes. An important enlargement of wafer bonding applications field was brought by new developments in the area of low temperature wafer bonding processes (maximum temperature of 400{degree sign}C): with such processes wafer bonding can be applied for fully patterned wafers (e.g. CMOS), IC wafers (e.g. for 3D interconnects) or silicon direct bonding can now be performed in standard industrial wafer bonding equipment. Plasma activated wafer bonding is a process in which the two substrates are submitted to a plasma treatment prior to bringing them into contact. This surface treatment allows the control of surface chemistry and results in obtaining a high bond strength at low annealing temperatures and short thermal annealing times. This paper reports new results obtained for different applications using plasma activated wafer bonding.

Plasma activated wafer bonding generated a high interest in last decade due to the important process temperature reduction. With the main advantage of bringing some applications at industrial degree of feasibility. An example of process which benefits from this new process is silicon fusion bonding: by using plasma activation the bond process temperature and time are reduced at values which make wafer bonding compatible with industrial manufacturing requirements. A newly developed process allowing bonding of two substrates in the plasma activation chamber is foreseen as a very interesting approach for numerous applications, especially in the field of engineered substrates fabrication.