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Code converters are essential in digital nano communication; therefore, a low-complexity optimal QCA layout for a BCD to Excess-3 code converter has been proposed in this paper. A QCA clock-phase-based design technique was adopted to investigate integration with other complicated circuits. Using a unique XOR gate, the recommended circuit's cell complexity has been decreased. The findings produced using the QCADesigner-2.0.3, a reliable simulation tool, prove the effectiveness of the current structure over earlier designs by considering the number of cells deployed, the area occupied, and the latency as design metrics. In addition, the popular tool QCAPro was used to estimate the energy dissipation of the proposed design. The proposed technique reduces the occupied space by ∼ 40%, improves cell complexity by ∼ 20%, and reduces energy dissipation by ∼ 1.8 times (at γ = 1.5EK) compared to the current scalable designs. This paper also studied the suggested structure's energy dissipation and compared it to existing works for a better performance evaluation.