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This article presents a mixed-computation neural network processing approach for edge applications that incorporates low-precision (low-width) Posit and low-precision fixed point (FixP) number systems. This mixed-computation approach uses 4-bit Posit (Posit4), which has higher precision around 0, for representing weights with high sensitivity, while it uses 4-bit FixP (FixP4) for representing other weights. A heuristic for analyzing the importance and the quantization error of the weights is presented to assign the proper number system to different weights. In addition, a gradient approximation for Posit representation is introduced to improve the quality of weight updates in the backpropagation process. Due to the high energy consumption of the fully Posit-based computations, neural network operations are carried out in FixP or Posit/FixP. An efficient hardware implementation of an MAC operation with a first Posit operand and FixP for a second operand and accumulator is presented. The efficacy of the proposed low-precision mixed-computation approach is extensively assessed on vision and language models. The results show that on average, the accuracy of the mixed-computation is about 1.5% higher than that of FixP with a cost of 0.19% energy overhead.

Single Flux Quantum (SFQ) technology represents a groundbreaking advancement in computational efficiency and ultra-high-speed neuromorphic processing. The key features of SFQ technology, particularly data representation, transmission, and processing through SFQ pulses, closely mirror fundamental aspects of biological neural structures. Consequently, SFQ-based circuits emerge as an ideal candidate for realizing Spiking Neural Networks (SNNs). This study presents a proof-of-concept demonstration of an SFQ-based SNN architecture, showcasing its capacity for ultra-fast switching at remarkably low energy consumption per output activity. Notably, our work introduces innovative approaches: (i) We introduce a novel spike-timing-dependent plasticity mechanism to update synapses and to trace spike-activity by incorporating a leaky non-destructive readout circuit. (ii) We propose a novel method to dynamically regulate the threshold behavior of leaky integrate and fire superconductor neurons, enhancing the adaptability of our SNN architecture. (iii) Our research incorporates a novel winner-take-all mechanism, aligning with practical strategies for SNN development and enabling effective decision-making processes. The effectiveness of these proposed structural enhancements is evaluated by integrating high-level models into the BindsNET framework. By leveraging BindsNET, we model the online training of an SNN, integrating the novel structures into the learning process. To ensure the robustness and functionality of our circuits, we employ JoSIM for circuit parameter extraction and functional verification through simulation.

In this article, we introduce GEMA, a genome exact mapping accelerator based on learned indexes, specifically designed for FPGA implementation. GEMA utilizes a machine learning (ML) algorithm to precisely locate the exact position of read sequences within the original sequence. To enhance the accuracy of the trained ML model, we incorporate data augmentation and data-distribution-aware partitioning techniques. Additionally, we present an efficient yet low-overhead error recovery technique. To map long reads more efficiently, we propose a speculative prefetching approach, which reduces the required memory bandwidth. Furthermore, we suggest an FPGA-based architecture for implementing the proposed mapping accelerator, optimizing the accesses to off-chip memory. Our studies demonstrate that GEMA achieves up to 1.36 × higher speed for short reads compared to the corresponding results reported in recently published exact mapping accelerators. Moreover, GEMA achieves up to ∼22 × faster mapping of long reads compared to the available results for the longest mapped reads using these accelerators.

In this work, to limit the number of required attention inference hops in memory-augmented neural networks, we propose an online adaptive approach called $\text{A}^{2}\text{P}$ -memory-augmented neural network (MANN). By exploiting a small neural network classifier, an adequate number of attention inference hops for the input query are determined. The technique results in the elimination of a large number of unnecessary computations in extracting the correct answer. In addition, to further lower computations in $\text{A}^{2}\text{P}$ -MANN, we suggest pruning weights of the final fully connected (FC) layers. To this end, two pruning approaches, one with negligible accuracy loss and the other with controllable loss on the final accuracy, are developed. The efficacy of the technique is assessed by applying it to two different MANN structures and two question answering (QA) datasets. The analytical assessment reveals, for the two benchmarks, on average, 50% fewer computations compared to the corresponding baseline MANNs at the cost of less than 1% accuracy loss. In addition, when used along with the previously published zero-skipping technique, a computation count reduction of approximately 70% is achieved. Finally, when the proposed approach (without zero skipping) is implemented on the CPU and GPU platforms, on average, a runtime reduction of 43% is achieved.

This paper proposes a design-for-testability (DFT) scheme and a test method to improve the detection of hard-to-detect (HtD) faults of STT-MRAMs. The proposed DFT scheme considers HtD faults which are undefined state faults (USFs). These states do not always lead to incorrect functionality during the test process resulting in test escapes. The proposed DFT scheme, which can be deployed as a standalone technique, is called USFA-DFT (an undefined state fault-aware design-for-testability technique). In this scheme, the USF detection is achieved through using a weak write before reading the cell. The weak write overwrites defective cells, causing an incorrect read output, without flipping the content of defect-free cells. To avoid test escapes or yield loss (over-testing) caused by process variation (PV) effects, we make use of a post-silicon calibration scheme. Next, to improve the detectability of HtD faults in STT-MRAMs, we suggest a hybrid high coverage test method (called H2C-TM) which enhances the previous method called LCHC-DFT (a low-cost high-coverage design-for-testability technique) by combining it with USFA-DFT. This test method improves the HtD fault detection, by applying the weak write (controlled by USFA-DFT) before the stressed read operation (controlled by LCHC-DFT). This hybrid approach has a negligible area overhead (3.18% for a 1 kbit array). The results for the performance evaluation of the H2C-TM scheme show that for intra-cell and inter-cell defects, on average, the improvements of 14.4% and 11.3% of HtD fault coverage, compared to those of LCHC-DFT, are achieved. Also, for intra-cell and inter-cell defects, the proposed hybrid approach outperforms USFA-DFT by 49.8% and 49.3% respectively. Finally, in the presence of the process variation, the proposed test method guarantees a robust DFT with only a maximum deviation of 10% from the nominal value.

This paper proposes a low-cost yet high-coverage design-for-testability (DFT) scheme for improving the detection of hard-to-detect (HtD) faults in STT-MRAMs. It is based on introducing a voltage mismatch in the sense amplifier (SA). This mismatch along with the defects in the cell may bias the SA, leading to an incorrect read output which in turn make the HtD faults detectable. The efficacy of the proposed scheme is evaluated by calculating its detection capability in the presence of resistive defects. Evaluation results obtained for a 20nm STT-MRAM memory design show that the proposed scheme provides HtD fault coverage of 81.8% and 86.5%, on average, for intra-cell and inter-cell defects, respectively, with a negligible area overhead (1.1% for a 2Kbit array). In comparison with conventional March tests, which only detect easy-to-detect (EtD) faults, the proposed DFT technique covers both HtD and EtD faults with a faster approach, namely by using a single read operation. Furthermore, to guarantee that the cells affected by HtD faults trigger an incorrect read output under process variation (PV), a timing strategy based on modifying the control unit of the proposed DFT is suggested. The strategy controls the stress introduced by the DFT unit by altering the timing of DFT control signals. The timing alteration enables the detection of HtD faults in the devices with higher deviations from the nominal one due to PV, avoiding yield loss or test escapes.

An energy–quality scalable coarse grain reconfigurable architecture (CGRA) based on the voltage overscaling (VOS) technique is presented. The approximation level of each processing element (PE) in the CGRA is determined by the applied VOS-determined voltage level. By employing the technique, the architecture may be configured for accurate or approximate modes of computation depending on a user-specified output quality-of-service target for a given application. More precisely, operating voltages used for performing various operations in the application dataflow graph are minimized subject to the output quality constraint by using an energy–quality tradeoff algorithm. To make the hardware implementation of the scheme more efficient, PEs are clustered into groups of (e.g., $3\times 1$ and $2\times 1$ ) voltage islands. To assess the efficacy of the proposed method in improving the power (energy) consumption and reliability of CGRAs, different combinations of minimum output quality constraints, voltage levels, and cluster sizes for several benchmarks are studied. Simulation results indicate considerable reductions in energy consumption (up to 43%) and aging rate (up to 73%) when compared with the conventional CGRA with perfect output quality (i.e., with no approximate computations).

In this article, we present a critical path selection method that efficiently finds true (sensitizable) critical paths of a circuit in the presence of process variations. The method, which is based on the viability analysis, tries to select the least number of true critical paths that cover all of circuit critical gates. Critical gates are those that make a path critical with a probability higher than a predefined threshold value. Selecting fewer critical paths leads to less computation time for the algorithm and shorter test time of fabricated chips. For this purpose, an efficient Statistical Static Timing Analysis– (SSTA) based technique is suggested. This technique tries to find circuit-critical gates whose process parameter variations cover a major part of the process space. Improving the process space coverage using fewer paths is achieved by considering both spatial (proximity of gates) and structural (having common gates) correlations in the analysis of choosing the critical paths. In the selection process, paths with low similarities in their characteristics are preferred. In addition, only true paths whose delays affect the maximum delay of the circuit are included. The selected paths can be used in the test process of the fabricated chips to determine if the chip meets its timing requirements. Also, a modified viability analysis that incorporates statistical computations is used in the SSTA. The efficacy of the proposed method is evaluated by comparing its results for combinational and sequential ISCAS benchmarks with those obtained by exhaustive search. Results indicate although, on average, only 4.38% of all the critical paths found by the exhaustive search are selected by the proposed method, the maximum probability of criticality for the paths that are not considered in our method is, on average, less than 4%.

In this article, we investigate the application of different techniques for mitigating the impact of process variations on the custom functional unit (CFU) of extensible processors. The techniques include using extra cycles for the CFU and extending the clock period for the extensible processor. The former technique is based on providing an extra clock cycle to those custom instructions (CIs) that have timing yields smaller than one. For this purpose, we make use of a lookup table (LUT) for each fabricated processor. Based on a post-fabrication analysis, the need for an extra clock cycle for some CIs is determined. Consequently, the CI timing violations are prevented, and all manufactured extensible processors will work with a predefined clock cycle time. To study the effect of the objective function (used during the CI selection phase) on the efficacy of the suggested architectural technique, we investigate three different objective functions. In the second technique, the clock period extension is used to guarantee a design yield of one. Our results demonstrate that combining both techniques helps increase the speedup achieved by the extensible processor. To assess the efficacies of the proposed methods, several benchmarks from different application domains are used. Results of the study reveal that the suggested techniques provide considerable improvements in the speedups of the extensible processors when compared to those of approaches that do not consider the impact of process variations.