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Scanning acoustic microscopy (SAM) technique has been applied to defect inspection in electronic devices. With the increase of packaging density, detection of the micro-defects in high density devices becomes more and more challenging. The SAM test is suffering from sacrificing the spatial resolution to reach a certain penetration depth of the ultrasonic waves. So it is necessary to enhance the resolution level of the SAM image. In this paper, a wavelet based resolution enhancement technique was investigated to reconstruct a high quality image for SAM test of the flip chip packages. The stationary wavelet transform was adopted to decompose the captured SAM image into four frequency subbands, and the high frequency subbands were enhanced by adding the difference matrix in the intermediate stage, and a super resolution SAM image was derived from combining all the subbands by using the Inverse Discrete Wavelet Transform. Then the solder joints segmented from the SR-SAM image were classified by using the SVM algorithm. The results validated that the proposed technique is effective to improve the detection accuracy of SAM test. • An intelligent system is developed to inspect the solder joints of flip chip. • The SAM image is decomposed into four different frequency components. • High resolution SAM image is reconstructed with the wavelet-based method. • The solder joints are segmented from the SR-SAM image. • The SR-SAM image has high accuracy for defect recognition. [ABSTRACT FROM AUTHOR]

This paper presents the application of the principles of Flipped Classroom to the teaching of the construction of Force, Moment and Torque diagrams of a loaded shaft. Flipping the Classroom is a proposal in the context of Blended Learning which suggests that in-class students ' activities, supported by learning material made available to them in advance, could replace the traditional scheme of teacher led lectures followed by homework. Trying to take advantage of the benefits of Blended Learning, we introduced a Flipped Classroom within a Machine Design course of the Mechanical Engineering Educators Curriculum. [ABSTRACT FROM AUTHOR]

Sensor components may markedly differ from typical silicon chips. Consequently, versatile attachment methods are required for their interconnections. Anisotropic conductive adhesives (ACA) are interesting materials for attachments of sensors due to their versatility. In this study reliability of ACA attached humidity sensors was studied in hygrothermal conditions. The reliability of the interconnections was found to be excellent even under prolonged exposure showing that high reliability can be achieved with ACA materials in sensor applications. [ABSTRACT FROM AUTHOR]

As flip chip bonding has become a necessity for the packaging industry, fine-pitch bumping has also been widely studied. For the fine pitch solder bumping process, High Volume Solder on Pad (HV SoP) technology was developed using a novel maskless printing method. The height of a solder bump formed using HV SoP is about 10 µm higher than that of the solder resist on a PCB. For the new SoP process, we used a special material called a Solder Bump Maker (SBM). Using an SBM, which consists of resin and solder powder, uniform bumps can easily be made without a mask. To optimize the height of the solder bumps, various conditions such as the mask design, oxygen concentration, and processing method are controlled. In the present study, the single printing method functions only as a seed layer for HV SoP. Instead, a double printing method, which is a modification of a single printing method, is suggested. The average, maximum, and minimum heights of solder bumps obtained were 28.3, 31.7, and 26.3 µm, respectively. It is expected that the HV SoP process will reduce the costs for solder bumping and will be used for electrical interconnections in fine pitch flipchip bonding. [ABSTRACT FROM AUTHOR]

A novel interconnection technology based on a 52InSn solder was developed for flexible display applications. The display industry is currently trying to develop a flexible display, and one of the crucial technologies for the implementation of a flexible display is to reduce the bonding process temperature to less than 150°C. InSn solder interconnection technology is proposed herein to reduce the electrical contact resistance and concurrently achieve a process temperature of less than 150°C. A solder bump maker (SBM) and fluxing underfill were developed for these purposes. SBM is a novel bumping material, and it is a mixture of a resin system and InSn solder powder. A maskless screen printing process was also developed using an SBM to reduce the cost of the bumping process. Fluxing underfill plays the role of a flux and an underfill concurrently to simplify the bonding process compared to a conventional flip-chip bonding using a capillary underfill material. Using an SBM and fluxing underfill, a 20 μm pitch InSn solder SoP array on a glass substrate was successfully formed using a maskless screen printing process, and two glass substrates were bonded at 130°C. [ABSTRACT FROM AUTHOR]

Demand for more interconnection joints between semiconductor devices can be realized with solder bump technology. Surface tension and density are usually material properties related factors that affect solder bump geometric shape. Therefore, to cope with this fast-changing microarchitecture design in semiconductor technology, a better understanding of the solder bump geometric shape is needed. This study used a static equilibrium force approach to integrate the surface tension and gravitational energy into the solder energy content. Surface Evolver software was used to perform calculations and deliver the final solder bump shape. Perfect agreement with less than 10 % comparison between previous studies and the current Surface Evolver results was found. According to statistical analysis using SPSS, the maximum width of solder shape is closely related to the surface tension. In contrast, the maximum standoff is highly correlated with the solder density. By changing the solder volume, the solder bump changes from standard flip-chip bump to Cu pillar bump with consistency in maximum width to maximum standoff height ratio of 1.5. This study shows that the bumping technology can produce various sizes of solder bumps to meet new electronic packaging requirements. [ABSTRACT FROM AUTHOR]

For the fine-pitch application of flip-chip bonding with semiconductor packaging, fluxing and hybrid underfills were developed. A micro-encapsulated catalyst was adopted to control the chemical reaction at room and processing temperatures. From the experiments with a differential scanning calorimetry and viscometer, the chemical reaction and viscosity changes were quantitatively characterized, and the optimum type and amount of micro-encapsulated catalyst were determined to obtain the best pot life from a commercial viewpoint. It is expected that fluxing and hybrid underfills will be applied to fine-pitch flip-chip bonding processes and be highly reliable. [ABSTRACT FROM AUTHOR]

No-flow underfill process has exhibited a narrow feasible process window due to electri-cal assembly yield loss or underfill voiding. In general, the assembly yield can be improved using reflow process designed at high temperature, while the high temperature condition potentially causes serious underfill voiding. Typically, the underfill voiding can result in critical defects, such as solders fatigue cracking or solders bridge, causing early failures in thermal reliability. Therefore, this study reviews a classical bubble nucleation theory to model voids nucleation during reflow process. The established model designed a reflow process possibly preventing underfill voiding. The reflow process was validated using systematic experiments designed on the theoretical study with a commercial high II O counts (5000>), fine-pitch (<150 pm) flip chip. The theoretical model exhibits good agreement with experimental results. Thus, this paper presents systematic studies through the use of structured experimentation designed to achieve a high, stable yield, and void-free assembly process on the classical bubble nucleation theory. [ABSTRACT FROM AUTHOR]

A novel bumping process using solder bump maker is developed for the maskless low-volume solder on pad (SoP) technology of fine-pitch flip chip bonding. The process includes two main steps: one is the aggregation of powdered solder on the metal pads on a substrate via an increase in temperature, and the other is the reflow of the deposited powder to form a low-volume SoP. Since the surface tension that exists when the solder is below its melting point is the major driving force of the solder deposit, only a small quantity of powdered solder adjacent to the pads can join the aggregation process to obtain a uniform, low-volume SoP array on the substrate, regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 µm is successfully formed. [ABSTRACT FROM AUTHOR]

Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials (TIMs), second level ceramic ball grid array (CBGA) solder joints, organic printed circuit board, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high coefficient of thermal expansion (CTE) ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/ speed), damage that can occur to the copperllow-k top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. In this work, test chips containing piezoresistive stress sensors have been used to measure the buildup of mechanical stresses in a microprocessor die after various steps of the flip chip CBGA assembly process. The utilized (111) silicon test chips were able to measure the complete threedimensional stress state at each sensor site being monitored by the data acquisition hardware. Special test fixtures were developed to eliminate any additional stresses due to clamping effects. The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, and lid attachment). The experimental observations from this study show clearly that large area array flip chips are subjected to relatively large compressive in-plane normal stresses after solder reflow. We also observed that the majority of the die compressive stress is accumulated during the underfilling assembly step. Typical increases in the stress magnitude were on the order of 300% (relative to the stresses due to solder joint reflow only). As a general "rule of thumb," approximately two-thirds (∼66%) of the final die stress magnitudes were observed to be developed during the underfill dispense and cure, with the second largest contribution coming from the die attachment, and the smallest contribution coming from lid attachment. The experimental test chip stress measurements were correlated with finite element simulations of the packaging process. A sequential modeling approach has been utilized to predict the build-up of compressive stress. The utilized method incorporates precise thermal histories of the packaging process, element creation, and nonlinear temperature and time dependent material properties. With suitable detail in the models, excellent correlation has been obtained with the sensor data throughout all packaging processes. Finally, CBGAs with the stress sensing chips were soldered to organic printed circuit board (PCB) test boards. A simulated heat sink loading applied, and the stresses were measured as a function of the clamping force. Compressive stress changes of up to -- 60 MPa were observed for a 1000 N applied clamping force. The experimental test chip stress measurements were correlated with finite element simulations of the clamping process. With suitable detail in the models, excellent correlation has been obtained for the stress changes occurring during simulated heat sink clamping. [ABSTRACT FROM AUTHOR]

Since the thickness of stacked silicon chips in 3D integration has been thinned to less than 100 &mgr;m, the local thermal deformation of the chips has increased drastically because of the decrease of the flexural 'rigidity of the thinned chips. The clear periodic thermal deformation and thus, the local distribution of thermal residual stress appears in the stacked chips due to the periodic alignment of metallic bumps, and they sometimes deteriorate mechanical and electrical reliability of electronic products. In this paper, the dominant structural factors of the local residual stress in a silicon chip are investigated quantitatively based on the results of a three-dimensional finite element analysis and the measurement of the local residual stress in a chip using stress sensor chips. The piezoresistive strain gauges were embedded in the sensor chips. The length of each gauge was 2 &mgr;m, and an unit cell consisted of four gauges with different crystallographic directions. This alignment of the strain gauges enables us to measure the tensor component of threedimensional stress fields separately. Test flip chip substrates were made of silicon chip on which the area-arrayed tin/ copper bumps were electroplated. The width of a bump was fixed at 200 &mgr;m, and the bump pitch was varied from 400 &mgr;m to 1000 &mgr;m. The thickness of the copper bump was about 40 &mgr;m and that of tin layer was about 10 &mgr;m. This tin layer was used for the formation of rigid joint by alloying it with copper interconnection formed on a stress sensing chip. The measured amplitude of the residual stress increased from about 30 MPa to 250 MPa depending on the combination of materials such as bump, underfill, and interconnections. It was confirmed that both the material constant of underfill and the alignment structure of fine bumps are the dominant factors of the local deformation and stress of a silicon chip mounted on area-arrayed metallic bumps. It was also confirmed that not only the control of mechanical properties of electroplated copper thin films, but also the hound' s-tooth alignment of a through silicon via and a bump are indispensable for minimizing the packaging-induced stress in the three-dimensionally mounted chips. This test chip is very effective for evaluating the packaging-processinduced stress in 3D stacked chips quantitatively. [ABSTRACT FROM AUTHOR]

Copper-silver (Cu-Ag) composite flip-chip interconnect between silicon (Si) chips and Cu substrates is demonstrated. Array of Cu-Ag columns, each 28 &mgr;m in height and 40 &mgr;m in diameter, is electroplated on 2-in. Si wafers coated with chromium (Cr)/gold (Au) dual layer. The Si wafers are diced into 6 mm x 6 mm chips, each containing 50 x 50 Cu-Ag columns. The Si chip with Cu-Ag columns is bonded to Cu substrates at 260 &Deg;C in 80 mTorr vacuum. A bonding force of only 1.8 kg is applied, corresponding to 0.71 g per Cu-Ag column. During bonding, Ag atoms in Cu-Ag columns deform and their surfaces conform to and mate with the surface of Cu substrate. Solid-state bonding incurs when Ag atoms in Cu-Ag columns and Cu atoms in Cu substrates are brought within atomic distance so that they share conduction electrons. The Cu-Ag columns are indeed bonded to the Cu. No molten phase is involved in the bonding. The joint consists of 60% Cu section and 40% Ag section. The ductile Ag is able to accommodate the thermal expansion mismatch between Si and Cu. The Cu-Ag joints do not contain any intermetallic compound (fMC). This interconnect technology avoids all reliability issues associated with fMC growth in conventional soldering processes. Compared to tin-based lead-free solder joints, Cu-Ag composite joints have superior electrical and thermal properties. [ABSTRACT FROM AUTHOR]

Solder self-alignment is an important phenomenon enabling cost-effective optoelectronics assembly. In thts study, the wetting of Sn-rich solder to under bump metallization (UBM) pads is identified as a cntzcal factor affecting self-alignment accuracy. Incomplete wetttng of solder to the metallization pads is responsible for chip-to-substrate misalignment larger than 1 &mgr;m, whzle fabncatwn tolerances, such as solder volume variation and pad diameter deviation, only account for misalignments in the submicron range. To quantitatively investigate the effect of incomplete wetting on self-alignment accuracy, a threedzmensional (3D) model based on a force optimization method was developed. With the input parameters of incomplete solder metallurgical wetting area, position and diameter of metallization pad, volume of individual solder bumps, coefficient of solder surface tension, mass of the chip, external forces acting on the chip, and initial pick-and-place position of the chip before assembly, the model predicts the assembled position of the chip in terms of the misalignments in the X-Y plane and the rotation angle along the Z axis. The model further confirmed that incomplete wetting of solder is the most critical modulator among the undesirable factors affecting solder self-alignment accuracy. [ABSTRACT FROM AUTHOR]

In this paper, the finite volume method (FVM) is used for the simulation offlip chip underfill process by considering non-Newtonian flow between two parallel plates that emulate the silicon die and the substrate. 3D model of two parallel plates of size 12.75 mm x 9.5 mm with gap heights of 5 pm, 15 pm, 25 pm, 35 pm, 45 pm, and 85 pm are developed and simulated by computational fluid dynamic (CFD) code, FLUENT 6.3.26. The flow is modeled by using power law model and volume of fluid (VOF) technique is applied for flow front tracking. The effect of change in height of the gap between the plates on the underfill process is mainly studied in the present work. it is observed that the gap height has significant influence on the melt filling time and pressure drop, as the gap height decreases filling time and pressure drop increase. The simulation results are compared with previous experimental results and found in good conformity. [ABSTRACT FROM AUTHOR]

Abstract: Solder bump inspection of flip chip has gained more attention with the widely use of flip chip package technologies in microelectronics packaging industry. A non-destructive testing method using ultrasonic excitation and modal analysis was presented for the detection of solder bump missing, a typical defect occurred in flip chip. The flip chip with arrayed solder bumps is modelled, and the effect of solder bump missing on the modal frequencies is investigated. The shifting of the natural frequencies of the reference flip chips and defect flip chips are simulated and measured in the experiments. The analysis results of the theoretical calculation, simulation and experiments all reveal that the natural frequencies of defective chips are smaller than the ones of non-defective chips, which can be used for defective flip chips detection. Therefore, the modal analysis can be a useful tool for fault diagnosis of flip chip. [Copyright &y& Elsevier]

Formation of pure silver (Ag) flip-chip interconnect of silicon (Si) chips on copper (Cu) substrates is reported. Arrays of Ag columns, each 36 pm in height and 40 pm in diameter, are fabricated on 2-in. Si wafers which are first coated with chromium (Cr)/gold (Au) dual layers. The Si wafers are diced into 6 mm x 6 mm chips, each having 50 x 50 Ag columns. The Si chip with Ag columns is directly bonded to Cu substrate at 260 °C in 80 mTorr vacuum to inhibit oxidation. The static bonding pressure is as low as 680 psi (4.69 MPa), corresponding to a load of 0.021 oz (0.60 g) per column. During bonding, the Ag columns deform and conform to the Cu substrate. They are well bonded to the Cu. No molten phase is involved in the bonding process. The joints consist of pure Ag only. The ductile Ag joints are able to accommodate the thermal expansion mismatch between Si and Cu. It is well known that in nearly all soldering processes used in electronic industries, intermetallic compound (IMC) formation is essential to make a solder joint. In the pure Ag interconnect, no IMCs exist. Thus, reliability issues associated with IMCs are eliminated. Compared to tin-based lead-free solders, pure Ag joints have superior electrical and thermal properties. [ABSTRACT FROM AUTHOR]

A novel bumping material, which is composed of a resin and Sn3Ag0.5Cu (SAC305) solder power, has been developed for the maskless solder-on-pad technology of the fine-pitch flip-chip bonding. The functions of the resin are carrying solder powder and deoxidizing the oxide layer on the solder power for the bumping on the pad on the substrate. At the same time, it was designed to have minimal chemical reactions within the resin so that the cleaning process after the bumping on the pad can be achieved. With this material, the solder bump array was successfully formed with pitch of 150 μm in one direction. [ABSTRACT FROM AUTHOR]

The reliability of the flip chip package is strongly influenced by underfill, which has a much higher coefficient of thermal expansion (CTE) compared with other packaging materials and leads to large thermomechanical stresses developed during the assembly processes. Thermal expansion mismatch between different materials causes interface delamination between epoxy molding compound and silicon die as well as interface delamination between underfill and silicon die. The main objective of this study is to investigate the effects of underfill material properties, filet height, and silicon die thickness on the interface delamination between epoxy molding compound and silicon die during a lead-free solder reflow process based on the modified virtual crack closure method. Based on finite element analysis and experiment study, it can be concluded that the energy release rates at reflow temperature are the suitable criteria for the estimation of interface delamination. Furthermore, it is found that underfill material properties (elastic modulus, CTE, and chemical cure shrinkage), fillet height, and silicon die thickness can be optimized to reduce the risk of interface delamination between epoxy molding compound and silicon die in the flip chip ball grid array package. [ABSTRACT FROM AUTHOR]

The explosive growth in the use of the Internet and multimedia applications in both the home and the office has fueled the requirement for high-bandwidth communication systems capable of processing huge volumes of data in a prompt and reliable manner Plastic optical fiber (POF) has emerged as an ideal solution for meeting this requirement and is now speafled by many architects as a simple, one-cable solution for home and office data communication networks. This study presents a modified flip-chip light emit- ting diode (LED) package for use in short-distance, POF-based communication systems. In contrast to the planar surface of the traditional design, the proposed LED package has a curved boundary surface between the underfill and the air This boundary surface functions as a virtual lens, which focuses the light emitted by the LED into the acceptance cone of the optical fiber such that the amount of light coupled into the fiber core is maximized. The proposed design yields an average coupling efficiency of around 49.6% over an LED-optical core misalignment range of 0.4-3 mm. Furthermore, the curved boundary surface reduces the distance between the emitting source and the ambient environment; therefore, it improves the thermal dispersion efficiency of the LED package. [ABSTRACT FROM AUTHOR]

experiments were conducted in this paper to study the effect of Au/Ni/Cu or Cu substrate pad metallization on the electromigration reliability of 96.5Sn-3Ag-0.5Cu flip- chip solder joints with Ti/Ni( V)/Cu under bump metallurgy (UBM) under a current stressing condition with an average current density of around 5 kA / cm² at an ambient temperature of 150°C. Cross-sectional observations on current-stressed solder joints indicate that although Cu metallization results in severe voiding compared with Au/Ni/Cu metallization on the substrate side of the solder joint, the dominant failure has been identified as UBM consumption, and test vehicles with Cu metallization exhibit better electromigration reliability than those with Au/Ni/Cu metallization. The stronger durability against current stressing for test vehicles with Cu metallization may attribute to the lower UBM consumption rate due to the continuous Cu diffusion toward U/3M as a result of the concentration gradient. The consumption of UBM is faster for test vehicles with A u/Ni/Cu metallization because Cu diffusion from the substrate pad is retarded by the Ni barrier. [ABSTRACT FROM AUTHOR]

A flip-chip interconnect configuration with coplanar strip (CPS) lines on printed circuit boards (PCBs) is reported for millimeter-wave applications. For CPS lines, the signal and ground electrodes both lie on the top surface of a chip or substrate. The flip-chip configuration was designed and implemented using a test chip on a dielectric board. Geometrical parameter analysis was carried out using full-wave simulation and equivalent circuit model for wideband performance. The chip was connected to the board using solder bumps. For a typical flip-chip assembly, the measured insertion loss is less than 3 dB for frequencies of up to 35 GHz and the return loss is higher than 15 dB for frequencies of up to 29 GHz using CPS flip-chip configuration. [ABSTRACT FROM AUTHOR]

The occurrence of passivation-underfill interfacial delamination is detrimental to the reliability of the flip chip assembly as it can result in the premature cracking of the solder bumps. In this paper the propagation of delamination in a nanofilled no-flow underfill material from the chip passivation in flip chip assemblies has been assessed under accelerated thermal shock testing. A theoretical model of the flip chip assembly has been developed, and the delamination occurring at the silicon nitride (SiN)-underfill interface has been studied under monotonic as well as the rmomechanical fatigue loading. Using empirical models for delamination propagation, the growth of delamination under monotonic as well as thermomechanical fatigue loading in a flip chip assembly has been predicted. These predictions agree well with the thermal shock cycling experimental data. The agreement between the theoretical predictions and experimental data suggests that the models and the methodology developed in this work can be used to design flip chip assemblies with nanofillled no-flow underfill materials against interfacial delamination. [ABSTRACT FROM AUTHOR]

Experimental and numerical techniques are employed to assess the thermomechanical behavior of ceramic and organic flip chip packages under power cycling (PC) and accelerated thermal cycling (ATC). In PC, nonuniform temperature distribution and different coefficients of thermal expansion of each component make the package deform differently compared to the case of ATC. Traditionally, reliability assessment is conducted by ATC because ATC is believed to have a more severe thermal loading condition compared to PC, which is similar to the actual field condition. In this work, the comparative study of PC and ATC was conducted for the reliability of board level interconnects. The comparison was made using both ceramic and organic flip chip ball grid array packages. Moire interferometry was adopted for the experimental stress analysis. In PC simulation, computational fluid dynamics analysis and finite element analysis are performed. The assembly deformations in numerical simulation are compared with those obtained by Moire images. It is confirmed that for a certain organic package PC can be a more severe condition that causes solder interconnects to fail earlier than in ATC while the ceramic package fails earlier in ATC always. [ABSTRACT FROM AUTHOR]

Underfill is usually modeled as an isotropic medium containing uniformly distributed filler particles. However filler particles tend to settle (or segregate) and thus alter the mechanical response of the flip chip die attachment package. The integrity of such flip chip attachment is different from that with an ideal, isotropic underfill with very uniform distribution of filler We analyzed the thermomechanical implications offiller settling to the stresses along the die/underfill interface by considering different profiles for the local concentration offiller and calculating their effective material properties by employing the Mon-Tanaka method. As the worst-case scenario, direct silicon die attach with solder bumps was assumed to analyze the intetfacial stresses, which were predicted in trend by a simplified multilayered stack model and calculated in detail by finite element simulation. The filler settling has a localized but strong influence on the intetfacial peeling stress near the edge of the die. The extent of this influence is detennined by the profile of filler settling: (1) if the filler is assumed to settle in the form of a bilayer then the peeling stress near the die's edge increases and it is directly proportional to the average volume fraction of the filler; (2) if the filler is assumed to settle gradually, then the magnitude of the peeling stress near. the edge of the die becomes smaller as the local filler volume fraction near the die interface increases. The filler settling has no significant effect on the other components of the interfacial stresses. The edge fillet of underfill in pure resin can locally reverse the direction of the interfacial peeling stress and increase the interfacial shearing stress near the die's edge. [ABSTRACT FROM AUTHOR]

The physics explored in this investigation enables short-time scale dynamic phenomenon to be correlated with package failure modes such as solder ball cracking and interlayer debond. It is found that although epoxy-based underfills with nanofillers are shown to be effective in alleviating thermal stresses and improving solder joint fatigue performance in thermal cycling tests of long-time scale, underfill material viscoelasticity is ineffective in attenuating short-time scale propagating shock waves. In addition, the inclusion of Cu interconnecting layers in flip chip area arrays is found to perform significantly better than Al layers in suppressing short-time scale effects. Results reported herein suggest that, if improved flip chip reliability is to be achieved, the compositions of all packaging constituent materials need be formulated to have well-defined short-time scale and Iong-time scale properties. Chip level circuit design layout also needs be optimized to either discourage or negate short-time wave propagation. The knowledge base established is generally applicable to high performance package configurations of small footprint and high clock speed. The approach along with the numerical procedures developed for the investigation can be a practical tool for realizing better device reliability and thus high manufacturing yield. [ABSTRACT FROM AUTHOR]

The reliability of fine pitch Sn-3.8Ag-0.7Cu flip chip solder joints with three different pads, i.e., bare pads, pads with solder masks, and pads with microvia, on printed circuit boards (PCBs) was studied through thermal cycling. After assembly, (Au,Ni)Sn4 intermetallics (IMCs) formed both in the bulk solder and at the interfaces due to the immersion-Au finish on the PCB side. The (Au,Ni)Sn4 IMCs formed in the solder joints on the pads with microvia were more abundant than those formed in the solder joints on the pads without microvia. The results showed that the solder joints on the pads with a microvia had poor reliability due to the insufficient solder volume and the formation of large amounts of (Au, Ni)Sn4 IMCs. The main crack initiation position was the corner of solder joint at the chip side. For the pads with microvia, the main location of failure was at the (Au, Ni)Sn4/solder interface on the chip side, and for the solder joints on bare pads and pads with solder mask, the possible failure location was in the bulk solder. [ABSTRACT FROM AUTHOR]

This paper systematically examines a method of reducing metastable (MS) operation in an edge-trigger type CMOS D flip-flop (EDFF) and a master-slave type D flip-flop (MDFF). To obtain a general idea, the mechanism of the MS operation of each flip-flop (FF) contained in the EDFF and MDFF has been classified into three types by using the results of a computer simulation. The first type MS operation is completely suppressed by the “differential threshold method” (in which the threshold voltage of the FF is different from that of the following circuit element so that the propagation of the MS operation is suppressed). An additional feedback method (by which the duration of the MS operation is reduced) is applied to the rest of the types of operations. A new circuit for these methods is also suggested. The computer simulation shows that the increase rate of MS-operation duration against the input-phase difference (difference between the occurrence time of a clock pulse and the occurrence time of an input) is reduced to about 1/4, and that the range of the input-phase difference of MS operations is reduced to about 1/3, in both EDFF and MDFF. © 2000 Scripta Technica, Syst Comp Jpn, 31(3): 20–28, 2000 [ABSTRACT FROM AUTHOR]

This study mainly focuses on site effects of the Ni pad interface on intermetallic compounds (IMCs) characteristic during assembly reflowing, and attempts to provide a reasonable explanation for this particular finding. Besides, the changes of the resulting IMCs characteristic are characterized during thermal shock (TS) cycling, and their potential influences on thermal-mechanical reliability of microjoints are evaluated experimentally and numerically. The results show that the site on the Ni pad interface of silicon chip has great influence on interfacial reaction products, i.e., interfacial IMCs. After bumps soldering, a great amount of larger diamond-shaped (Cu, Ni)6Sn5 compounds were densely packed at the edge region, while some smaller ones were only scattered at the center region. Moreover, substantial particle-shaped (Ni, Cu)3Sn4 compounds as well as some rod-shaped ones emerged at the spaces between the (Cu, Ni)6Sn5 compounds of the center region. More importantly, such site effects were remained in the microjoints during TS cycling, which induced the formation of larger protruding (Cu, Ni)6Sn5 compounds. Finite element (FE) simulation results showed that the stress was mainly concentrated at the top of the protruding (Cu, Ni)6Sn5 compounds, which can be a critical reason to cause the crack occurrence. Furthermore, the underlying mechanism of the interfacial IMCs characteristic induced by the site effects was attempted to propose during bumps soldering. [ABSTRACT FROM AUTHOR]

Low-temperature microjoining, such as wire (or ribbon) bonding, tape automated bonding (TAB), and flip chip bonding (FCB), is necessary for electronics packaging. Each type of microjoining takes on various aspects but has common bonding mechanisms regarding friction slip, plastic deformation, and friction heating. In the present paper, solid-state microjoining mechanisms in Au wire (ball) bonding, FCB, Al wire bonding (WB), and Al ribbon bonding are discussed to systematically understand the common bonding mechanisms. Ultrasonic vibration enhances friction slip and plastic deformation, making it possible to rapidly obtain dry interconnects. Metallic adhesion at the central area of the bonding interface is mainly produced by the friction slip. On the other hand, the folding of the lateral side surfaces of the Au bump, Au ball, and Al wire is very important for increasing the bonded area. The central and peripheral adhesions are achieved by a slip-and-fold mechanism. The solid-state microjoining mechanisms of WB and FCB are discussed based on experimental results. [ABSTRACT FROM AUTHOR]