Search

The physical unclonable function (PUF) is a hardware security primitive that is used to generate secret keys or identity authentication for chips using random manufacturing process variation (MPV). The PUF based on ring oscillator (RO PUF) has been extensively studied in recent years because of its high robustness and ease of design. Although the performance has been optimized in previous studies, several uniqueness, reliability, and theoretical foundation concerns still remain. This article presents a transistor-level parameters-based quantitative theoretical model, which clearly reveals several design guidelines for improving the reliability of RO PUF. Furthermore, a PUF based on a feedback ring oscillator (RO) structure is proposed, which combined the RO topology and the drafting effect of XOR gates to enhance the uniqueness and reliability. The correctness of the theoretical model was verified by the SPICE simulation experiment result. And in the FPGA experiment result, the uniqueness and the reliability of feedback RO PUF using the same hardware resources on the same chip was superior to that of RO PUF. The theoretical research method of RO PUF used can be widely applied to other PUFs using ring topology and feedback RO PUF is a great substitute for RO PUF.

The entropy source structure with embedded XOR gates in a ring oscillator (RO) as a true random number generator (TRNG) can improve the speed of accumulating jitter in the oscillator. However, the XOR gate has a certain response time to the input change, and when the input changes too fast, the XOR gate will output short pulses. In this paper, we propose a TRNG design based on a multi-ring convergence oscillator (MRCO) making use of the characteristics of short pulses. We study the output of the XOR gate when facing different inputs. By modeling the time of a fibonacci ring oscillator (FIRO) as an example, we find that the loss of short pulses in an inverter chain is the reason for making the FIRO enter into periodic oscillation. This phenomenon suppresses the accumulation of jitter and occurs periodically in existing structures. Our proposed structure uses independent sub-rings to accumulate jitter, allowing the main-ring to quickly generate short pulses to provide analog randomness. The proposed TRNG design is implemented in Xilinx Virtex-6 FPGA. The experimental results show that it has the highest ratio of throughput rate to hardware resources. The generated random sequence pass both NIST SP800-22 test and NIST SP800-90B test.