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The possibility to use semiconducting or metallic nanocrystals (ncs) embedded in a SiO2 matrix as charge storage elements in novel non volatile memory devices has been widely explored in the last ten years. The replacement of the continuous polysilicon layer of a conventional flash memory device by a 2-dimensional nanoparticle array presents several advantages but the fundamental trade-off between programming and data retention characteristics has not been overcome yet. The main problem is the limited retention time basically due to charge loss by leakage current through the ultra-thin SiO2 tunnelling dielectric. A longer retention time can be achieved by increasing the tunnel oxide thickness. This however implies higher operating voltages and consequently a reduced write/erase speed. Using high-k materials for tunnel and/or gate oxide it is in principle possible to achieve the goal of a low voltage non volatile memory device. The high dielectric constant of these materials allows using thicker tunnel oxide reducing leakage current. Several approaches have been explored to synthesise ordered arrays of ncs in SiO2 but the transfer of these methodologies to the synthesis of 2-d array of ncs in high-k materials is not trivial. In this work we address the material science issues related to the synthesis of metallic and semiconducting ncs in high-k materials using different techniques. A detailed review of the state of the art in the field is presented and further research strategies are suggested.

The possibility to use semiconducting or metallic nanocrystals (ncs) embedded in a SiO2 matrix as charge storage elements in novel non volatile memory devices has been widely explored in the last ten years. The replacement of the continuous polysilicon layer of a conventional flash memory device by a 2-dimensional nanoparticle array presents several advantages but the fundamental trade-off between programming and data retention characteristics has not been overcome yet. The main problem is the limited retention time basically due to charge loss by leakage current through the ultra-thin SiO2 tunnelling dielectric. A longer retention time can be achieved by increasing the tunnel oxide thickness. This however implies higher operating voltages and consequently a reduced write/erase speed. Using high-k materials for tunnel and/or gate oxide it is in principle possible to achieve the goal of a low voltage non volatile memory device. The high dielectric constant of these materials allows using thicker tunnel oxide reducing leakage current. Several approaches have been explored to synthesise ordered arrays of ncs in SiO2 but the transfer of these methodologies to the synthesis of 2-d array of ncs in high-k materials is not trivial. In this work we address the material science issues related to the synthesis of metallic and semiconducting ncs in high-k materials using different techniques. A detailed review of the state of the art in the field is presented and further research strategies are suggested.

In this paper, we have studied the evolution of quantum electronic features with the size of silicon nanoparticles embedded in an ultra-thin SiO2 layer. These nanoparticles were synthesized by ultralow energy (1 KeV) ion implantation and annealing. Their size was modified using the effect of annealing under slightly oxidizing ambient (N2+O2). Material characterization techniques including transmission electron microscopy (TEM) Fresnel imaging and spatially resolved electron energy loss spectroscopy (EELS) have been used to evaluate the effects of oxidation on structural characteristics of nanocrystal layer. Electrical transport characteristics have been measured on few (less than two hundred) nanoparticles by exploiting a nanoscale MOS capacitor as a probe. Top electrode of this nanoscale capacitor (100 nm x 100 nm) was patterned over the samples by electron-beam nanolithography. Room temperature I-V and I-t characteristics of these structures exhibit discrete current peaks which have been interpreted by quantized charging of the nanoparticles and electrostatic interaction between the trapped charges and the tunneling current. The effects of progressive oxidation on these current features have been studied and discussed.

In this paper, we present a study on the contribution of silicon nanocrystals to the electrical transport characteristics of large (100 [removed info]m x 100 [removed info]m) and small (100 nm x 100 nm) metaloxide- semiconductor (MOS) capacitors at room temperature. A layer of silicon nanocrystals is synthesized within the oxide of these capacitors by ultra-low energy ion implantation and annealing. Several features including negative differential resistance (NDR), sharp current peaks and random telegraph signal (RTS) are demonstrated in the current-voltage and current-time characteristics of these capacitors. These features have been associated to charge storage in silicon nanocrystals and to the resulting Coulomb interaction between the stored charges and the tunneling current. Clear transition from a continuous response of large capacitors to a discrete response of small capacitors reveals the quantized nature of the charge storage phenomenon in these nanocrystalline dots. The effect of the nanocrystal density from nearly continuous layer to isolated nanodots is also presented.

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Abstract: The Smart-Cut® process, based on ion implantation (hydrogen, helium) and wafer bonding, appears more and more as a generic process. The first part of the paper is dedicated to the specific case of thermally-induced splitting. Cavity growth by the Ostwald ripening mechanism and crack propagation are responsible for thermally-induced splitting. In this case, the splitting kinetics are controlled by hydrogen diffusion. In the second part, the latest results concerning new structures are presented.

AbstractIn this paper we present our binary collision Monte Carlo code that simulates ion implantation effects in semiconductor devices. The package composed of the Monte Carlo code and some other post-processors routines have been named IPROS (Ion Implantation PROcess Simulator). At the present stage IPROS is able to process amorphous targets presenting 10 atomic species and 10 different areas. The physical and computational aspects of the package are shortly elucidated. In this work IPROS is used to study phenomena like the damage profile dependency with mask opening width the estimation of the number of atomic species susceptible to be involved in the formation of end-of-range defects and finally we calculate a two-dimensional range distribution in a fictive source-drain junction.