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This paper is concerned with a high-speed, high-accuracy Hough transform which utilizes simultaneous recurrence formula. Existing methods of this kind still produce a small error in the ρ value calculation, and the ρ value does not agree well with the value calculated from the original Hough transform expression. Moreover, its form of expression is not adapted to parallel processing. The accuracy of the ρ value calculated by the new method provided in this paper is confirmed by computer simulation. The proposed method has also achieved very high calculation speed by replacing multiplication operations with the shift operations on the CPU registers. Because of its extremely simple configuration, it is easy to implement the algorithm in special hardware. It is suitable for parallel operation on the special hardware or a parallel processor. Thus, the newly proposed method assures a great progress in applying the Hough transform to real time processing. © 1997 Scripta Technica, Inc. Syst Comp Jpn, 28(3): 24–33, 1997 [ABSTRACT FROM AUTHOR]

Recently, due to remarkable technological developments and because their logic can be modified flexible and easily, Field Programmable Gate Arrays (FPGAs) have increasingly been applied to hardware prototyping and the design of restructurable computer architctures. For this reason, it is highly accessory to establish logic design techniques for FPGAs. This paper describes methods for optimizing the circuits mapped in look-up table-type FPGAs. These methods apply the concept of permissible functions from the transduction method, which s a logic circuit optimization technique based on design improvement, and attempt to reduce the degree of redundancy. The following two methods were investigated: 1) reducing the number of blocks by using a logic block to replace another; and 2) together with replacing logic blocks, modifying the internal logic that implements a logic block as long as the outputs are not affected. Although the latter generally is more flexible, the former requires less processing time and sometimes produces better results. The effectiveness of these methods is demonstrated by showing that the degree of redundancy was reduced by about 9 percent when the methods were applied to circuits mapped in look-up table-type FPGAs. The methods proposed in this paper can also be applied to designs using standard cells and gate arrays. [ABSTRACT FROM AUTHOR]

As the method to accelerate the learning by error back-propagation, several studies have been proposed in which the parameter called gain is introduced. In those studies, however, the acceleration effect is evaluated only numerically, and there is no theoretical analysis of the effect of the gain on the learning process. This paper points out that those studies can also be realized by methods without introducing the gain, and presents a detailed analysis of the effect of the gain from a unified viewpoint. The following properties are revealed as a result. The error back-propagation method, in which a constant gain is introduced, can be reduced to the ordinary error back-propagation method without introducing the gain. When the dynamic gain is introduced, the method cannot be reduced to the steepest descent method, as well as the momentum method, without introducing the gain. Furthermore, it is shown that there exists a characteristic superellipse that determines the behavior of the gain. By analyzing the characteristic superellipse, a theoretical basis is provided for the instability of the method introducing the dynamic gain. This paper presents a unified treatment of the method introducing the gain and the method not introducing the gain from a unified viewpoint which have been considered independently. The effect of the gain on the learning process is analyzed, which will help in developing a new learning method in the future. [ABSTRACT FROM AUTHOR]

This paper aims at: (1) improvement of the specification verification capability of SDI, without losing its advantages, i.e., transparency and descriptive power; and (2) realization of translation between specifications described by SDL and LOTOS. A method is proposed which gives a LOTOS interpretation of the specification by SDL. First, the mapping of the object system structure indicated by SDL specification to the LOTOS description is discussed. Then the description of the processing definition of SDL specification is described. Using the method proposed in this paper, a LOTOS interpretation is presented as an example for the SDL specification for the switching service. The result of interpretation is evaluated and the flexibility of the verification process is discussed. [ABSTRACT FROM AUTHOR]

fficiency and reliability are essential to microprograms, and it is important to perform debugging and evaluation through interaction with the simulator. The simulator is also indispensable in the development of the microprogram in parallel to the hardware. However, if a dedicated simulator is to be developed for each target computer, constraints are imposed on time and cost, making it difficult to realize a high-level interactive interface. On the ocher hand, if a general-purpose simulator is to be employed, it is difficult to provide an interface suited to the target computer, such as visual simulation. This paper proposes an object-oriented system aiming at the realization of both the detailed function of the dedicated simulator and the versatility of the software. Although the object-oriented language has a high modularity, adequate modeling must be provided for the whole system including the interlaces, to ensure the machine-independence of the microprogram simulator, where the object of the description itself depends on the target computer. In this paper, an interactive interface is proposed, which is suited to the debugging of the microprogram. Then a realization by the object-oriented scheme is described which has a high flexibility against the modification of hardware specification and permits an easy reuse of the software for other computers. As a practical example, the development of μP simutator by the authors is outlined, together with the description of the user interface. [ABSTRACT FROM AUTHOR]

Release planning for incremental software development assigns features to releases such that most important technical, resource, risk and budget constraints are met. The research presented in this paper is an element of a three-staged procedure. In addition to an existing method for (i) strategic release planning that maps requirements to subsequent releases and (ii) a more fine-grained planning that defines resource allocations for each individual release, we propose a third step, i.e. (iii) stability analysis, which analyzes fine-grained plans of individual releases with regard to their sensitivity to planning errors. Planning errors can relate to alterations in expected personnel availability and productivity, feature and task-specific work volume, and degree of task dependency. The focus of this article is on stability analysis of proposed release plans. We present the simulation model Release Plan Simulator, Version 1 (REPSIM-1) and illustrate its usefulness for stability analyses with the help of a case example. Copyright © 2007 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

SoftPM is a toolkit that supports a process-based approach to software project management. It relies upon a software process modeling method based upon the idea of an Organization-Entity to define standard processes and model project processes. The Process-Agent is the core of this modeling method and is a well-defined unit whose role is to encapsulate an Organization-Entity's knowledge, skill etc. The Process-Agent's infrastructure comprises descriptive knowledge, process knowledge and an experience library. The process knowledge is represented by process steps, whose execution determines the behaviors of the Process-Agent. This causes Process-Agent knowledge to be precisely described and well organized. In this paper, Little-JIL, a well-known process modeling language, is used to define a Process-Agent's process knowledge. Benefits for process element knowledge representation arising from Little-JIL's simplicity, semantic richness, expressiveness, formal and precise yet graphical syntax etc., are described. The article also demonstrates how this knowledge can be useful in supporting project planning activities, such as time estimation. Copyright © 2007 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

We proposed a control method for exchanging parts of an executing program. By applying this exchange method to a shared library that is linked dynamically, the contents of library functions that constitute the program can be changed without stopping processes that are providing services. In other words, maintenance tasks can be dynamically performed without suspending the services that are being provided. However, the program parts that are exchanged according to the proposed exchange method must satisfy strict exchange conditions, making it difficult to create program parts that are to be exchanged. Therefore, in this paper, we describe an exchange method in which the exchange conditions have been relaxed. Also, we point out a problem in which relaxing the exchange conditions causes the exchanging time to be significantly increased when exchanging parts for a program that is mainly a CPU-bound program compared with a program that is mainly an I/O-bound program. Then, to deal with this problem, we propose methods of devising process scheduling mechanisms to shorten the exchanging time. Specifically, we show a mechanism that temporarily suspends exchangeable processes early and a mechanism that preferentially executes unexchangeable processes. In addition, we implement and evaluate both of these mechanisms and show the effectiveness of each mechanism. © 2003 Wiley Periodicals, Inc. Syst Comp Jpn, 34(10): 13–25, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.10423 [ABSTRACT FROM AUTHOR]

This paper examines the expressional ability for partial interpretations of the class DF in data-flow schemes. It is assumed that each arc in the data-flow scheme, in a queue which can store any number of tokens. The class DF is compared with the class PAc of the program scheme in which an array can be used and suffices can be compared, and it is shown that PAc and DF realize the same class of functionals. This indicates that DF is equivalent in the ability the the class EFd of deterministic effective functionals, and, consequently, it has less ability than the class EF of the effective functionals. [ABSTRACT FROM AUTHOR]

For the purpose of providing higher reliability to multiple open-server computers in a distributed processing environment without changing platforms and application programs, we have developed QRM (Quick Rollback Module), an add-on module used to provide higher reliability based on checkpoints and the rollback mechanism. By adding QRM, computers recover from most transient hardware failures of nearby processors, from some permanent processor failures in multiprocessor computers, and from most panics caused by operating system hugs. QRM consists of hardware implemented as an attachment board and software implemented as loadable modules. With QRM installed, computers recover from failures within a few seconds; however, there exists a slight overhead in normal processing. Though the overhead changes according to the programs executed, the overhead in TPC-C bechmark is 10.9%. In this paper, we describe the implementation and the results of a performance evaluation of QRM. © 1998 Scripta Technica, Syst Comp Jpn, 29(4): 11–21, 1998 [ABSTRACT FROM AUTHOR]

Program slicing is a technique to extract from a program a set of statements (referred to as a slice) that have certain properties; such techniques are widely used, for example, for simplification and maintenance of software. This paper proposes a particular method to generate a slice that is formally represented by using a path dependence flow graph (PDFG), namely, by means of interpretive execution of the PDFG based on data-flow computation (1). Since the proposed method is a generalization of the conventional method of interpretive execution of PDFG based on data-flow computation, the same scheme of computation control can be employed as is used in other techniques of PDFG analysis, for example, infeasible path detection (2). The slicing algorithm is specified for nodes in the form of local rules. Therefore, by partially modifying those rules, new varieties of slices can be easily obtained, for example, more precise slices (3). During firing control in data-flow computation, executable nodes are found, and slice is generated simply by consecutive execution of rules at those nodes, which implies simple computation control (4). Since control of slicing can be distributed among nodes, parallel processing is possible (5). A generalized method that offers generation of slices not obtainable by conventional methods is proposed. © 1998 Scripta Technica, Syst Comp Jpn, 28(11): 22–33, 1997 [ABSTRACT FROM AUTHOR]

With previous active contour models (Snakes), separate extraction of multiple objects inside a contour was impossible, and thus the number of initial contours to be set was the same as that of objects. This paper aims at automatic extraction of multiple objects using Snakes, so that those objects can be extracted separately by means of a single initial contour that includes them all. For this purpose, a splitting contour model is proposed; specifically, a contraction-type Snake is split into multiple contours wherever self-crossing is detected during deformation by means of area term. With the proposed method, smaller contour models generated in splitting are extinguished, so that noise or nonrelevant tiny objects within the image are prevented from capturing; hence, stable extraction of objects is ensured even though the initial contour is placed well apart from the objects. Particularly, multiple objects may be extracted automatically with the initial contour set as the image border. Evaluation tests were carried out to prove the effectiveness of the proposed method, after which the method was applied successfully to actual images, namely, to extracting multiple cells from a microphotograph, and to extracting/tracing multiple objects from moving images. © 1998 Scripta Technica, Syst Comp Jpn, 28(11): 34–42, 1997 [ABSTRACT FROM AUTHOR]

Debugging of parallel programs is generally very difficult to undertake since the execution of programs is nondeterministic and nonrepeatable. Considering a parallel object-oriented language, this paper proposes a method of preserving the repeatability of the order of execution in a replay by defining a logic time in terms of events in the message communication system and state transitions, and by representing the execution history of events. A debugger that mainly uses a two-dimensional (2-D) representation and replay debugging has been designed based on the proposed method. A high-performance system has been constructed based on the design. The debugger functions are distributed between a host workstation and multicomputer nodes, and between local OS on nodes and in firmware so that a high-performance system has been realized. The experiments show that the method is successful for practical applications; the time and space overhead of event recording is 0.04 ms (mean value) and 35 B per event, respectively; the display of 16 objects for one logical time is 0.94 s; and the overhead for a breakpoint is 3.1 ms per point. © 1998 Scripta Technica, Syst Comp Jpn, 28(11): 53–63, 1997 [ABSTRACT FROM AUTHOR]

This paper considers the case where the specification and the program are modified. A method is proposed that specifies the range which is affected by the modification using the verification method and decomposition technique. By the proposed technique, the points where the modification is required or the point which may contain an error can be estimated when the program is modified. The inductive assertion is used as the verification technique. It is assumed that the specification before modification as well as the program are already verified for the correctness. The object of verification is simplified by the comparison and validation of the verification history and the object of correctness verification. The part which is left without being simplified is the range affected by the modification before the comparison and after the correctness verification, the rage which is affected by the modification as well as the range for which the validation is not satisfies can be specified. [ABSTRACT FROM AUTHOR]

Hypothetical reasoning is important to knowledge system framework due to both its theoretical basis and its usefulness in solving practical problems including diagnosis, design, etc. One crucial problem with hypothetical reasoning is, however, its slow inference speed. To achieve practical or tractable speed, an approximate solution method of 0-1 integer programming named Pivot and Complement has been applied so far to a cost-based hypothetical reasoning, in which a numerical weight is assigned to each possible element hypothesis and an optimal solution hypothesis-set with the minimal sum of its element hypotheses' weights is searched. In this method, all described knowledge is regarded as constraints. Then, the restricted part of knowledge is transformed into inequalities to apply 0-1 integer programming. While the computational complexity of hypothetical reasoning is NP-complete or NP-hard, an approximate solution method of 0-1 integer programming allows polynomial inference time in the order of N4 for finding a near-optimal solution hypothesis, where N is the number of possible element hypotheses. In this paper, in order to understand the mechanism of the foregoing method from the viewpoint of knowledge processing, it is reformalized using a new type of knowledge network. Our new networked method, name Networked Bubble Propagation is shown to have a similar (or superior) performance to the aforementioned one, i.e., the solutions it obtains are as good as those found with the Pivot and Complement method and the inference time is in the order of N². This speed-up is an advantage of considering the knowledge structure of a given problem, thanks to the network. [ABSTRACT FROM AUTHOR]

The authors have been developing a distributed operating system called Threads on Modules (ToM). It supports a programming model which is suited for distributed environments. For this purpose, modules, threads, houses, users, RPCs and capabilities are introduced. To make the ToM system as portable as possible, it was implemented using the microkernel technology. The ToM microkernel implements the minimal functionalities and the others are implemented as user level programs. Although the ToM microkernel is designed to support the ToM programming model, it has sufficient functionalities to implement other operating systems. This paper presents some of the main features of the ToM microkernel. A UNIX emulator also is presented. [ABSTRACT FROM AUTHOR]

When selecting the set of conditions to be tested in modular white-box testing of fundamental program functions, various kinds of criteria are available, including the branch coverage criterion and the all-uses criterion. But there has been very little research on the relationship of these criteria to the overlooking of program faults, and as a consequence many program faults have been discovered only in the later phases of development or at customer sites, where conditions not covered by the original testing occurred. In this paper, an attempt is made to identify the relationship between test conditions and program fault overlooks by expressing the data flows of the program as chains of define-use relationships between two variables. The approach is tested on commercial software products for the control of measuring equipment. The results are used to develop a method of choosing test paths so as to prevent the principal overlook types, and the detection ability and computational efficiency are compared with those of conventional selection criteria. The number of test required in the new method is comparable with that in the all-uses method, and it is capable of preventing almost all of the overlooks that arise from the method used for test path selection. [ABSTRACT FROM AUTHOR]

A programmer modifies software for various reasons, e.g., a change of its requirements or bug correction. When a modification is made in the software, the effect of the modification propagates to various points of the software. Such side effects must be corrected. By automating the correction procedure for the effects produced by the modification, the productivity and the reliability of the software development will be improved. This paper discusses the software modification support and proposes an automatic method of correction for the type modification in the program. The modification support system developed based on the proposed idea is described. [ABSTRACT FROM AUTHOR]

This paper proposes a concurrent description language called NCC for scientific calculations that are executed on a multiprocessor. NCC is based on a static concurrent process model called "NC model." NCC's minimal features allow scientific calculations to be efficiently executed on a large- scale multiprocessor. Having obtained less overhead in execution by restricting NCC's ability to describe concurrent processes, NCC allows users to write scientific calculation programs which are both highly easy to analyze and read. [ABSTRACT FROM AUTHOR]

This paper presents an extended graph grammar, called a logic hypergraph grammar (LHG), and discusses its capabilities and parsing method. This grammar generates hypergraphs by resolution in logic programming and is intended to be a basis for analyzing and recognizing general structures by logic programming. An LHG is called a context-free hypergraph grammar (CFHG) if each production rule represents a replacement of a hyperedge by a subhypergraph. Several normal forms are presented for CFHG and for a hierarchy on subclasses of languages of CFHGs with respect to the maximum number of vertices in nonterminal hyperedges. Finally, a parsing method of LHG using Prolog is presented. [ABSTRACT FROM AUTHOR]

To evaluate the reliability of software quantitatively, a test is executed at the final stage of software development. Then errors existing in the software are corrected. In the testing phase, the functions and nodules actually tested in the software are related closely to the quantity and quality of the imposed test case, and increase with the progress of the testing. In this paper, the set of functions and modules affected by the test in the software is called testing-domain. A software reliability growth model is discussed, where the increase/expansion of the testing-domain is assumed to he related to the error detection of the software errors. A result is shown where the model is applied to the actual software error data. A comparison is made from the viewpoint of matching with other software reliability growth models. [ABSTRACT FROM AUTHOR]

Functional languages are known to have such advantages as simply defined semantics. However little study has been made regarding compilation or optimization methods for efficient execution on a conventional machine. This paper formulates some optimization methods compiling a functional language ASL/F program into an object program in a procedural language, and further gives some sufficient conditions to perform these optimizations. It introduces "needed-arguments first computation" and "globalization of sorts (data types)," which are new optimization methods and have not been discussed before. Sample programs which are compiled and executed by an experimental compiler perform these optimization methods, as well as elimination of duplicated computation for common subterms, elimination of tail recursion, and rewriting in compilation. These experimental results show that execution time and dynamic memory space requirement of the object program are reduced by these optimizations and the program can be executed in almost the same time as an equivalent program written in a procedural language such as PASCAL. [ABSTRACT FROM AUTHOR]