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2. Skyway: Accelerate Graph Applications with a Dual-Path Architecture and Fine-Grained Data Management
3. Functionalism, integrity, and digital consciousness
4. Irregular accesses reorder unit: improving GPGPU memory coalescing for graph-based workloads
5. A New High-Speed, Low-Area Residue-to-Binary Converter For the Moduli Set {24n,22n+1,2n+1,2n-1} Based on CRT-1
6. High-Performance System-on-Chip-Based Accelerator System for Polynomial Matrix Multiplications
7. Blockchain-based mobile fingerprint verification and automatic log-in platform for future computing
8. Reducing the second-level cache conflict misses using a set folding technique
9. The Sunway TaihuLight supercomputer: system and applications
10. Gem5v: a modified gem5 for simulating virtualized systems
11. Exploiting Tightly-Coupled Cores
12. A memristor-based architecture combining memory and image processing
13. Adaptive prefetching using global history buffer in multicore processors
14. A Fast Architecture for H.264/AVC Deblocking Filter Using a Clock Cycles Saving Process
15. Instructions and hardware designs for accelerating SNOW 3G on a software-defined radio platform
16. A moving threads processor architecture MTPA
17. Dual-thread Speculation: A Simple Approach to Uncover Thread-level Parallelism on a Simultaneous Multithreaded Processor
18. Tolerating Radiation-Induced Transient Faults in Modern Processors
19. Physical Design Methodology for Godson-2G Microprocessor
20. Chip Multithreaded Consistency Model
21. CASA: A New IFU Architecture for Power-Efficient Instruction Cache and TLB Designs
22. Hardware architecture for RSA cryptography based on residue number system
23. Grid-Based Storage Architecture for Accelerating Bioinformatics Computing
24. Aligning the representation and reality of computation with asynchronous logic automata
25. A Scalable Interconnection Network Architecture for Petaflops Computing
26. A novel computer architecture to prevent destruction by viruses
27. A Low-Power Multithreaded Processor for Software Defined Radio
28. Research Progress of UniCore CPUs and PKUnity SoCs
29. Discrete Wavelet Transform: Architectures, Design and Performance Issues
30. Towards a neurally-inspired computer architecture
31. FlexCore: Utilizing Exposed Datapath Control for Efficient Computing
32. Wireless multi-hop network scenario emulation by controlling maximal error
33. Intrinsic Compiler Support for Interval Arithmetic
34. Application-specific Processor Architecture: Then and Now
35. Finding the Next Computational Model: Experience with the UCSC Kestrel
36. Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors
37. Compiler Techniques for the Superthreaded Architectures1, 2
38. Selective Branch Inversion: Confidence Estimation for Branch Predictors
39. Construction of a reconfigurable dynamic logic cell
40. Fault-tolerant design techniques in A CMP architecture
41. SCMP: A Single-Chip Message-Passing Parallel Computer
42. Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects
43. Quantitative analysis of hardware support for real-time operating systems
44. Rechnersysteme für Internet und Intranet
45. Parallel Implementation of Self-Organizing Map on the Partial Tree Shape Neurocomputer
46. The M-machine multicomputer
47. Pipelining in der Rechnerarchitektur
48. Sequential architecture models for Prolog: A performance comparison
49. Sep: A Fixed Degree Regular Network for Massively Parallel Systems
50. Architectures massivement paralleles pour la vision artificielle
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