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Semiconductor materials have played a huge role in advancing today’s technology through the electronic and photonic devices ushered in over the years. The advancement has been driven in part by society’s growing need for electronic devices capable of handling higher power, higher temperature, and higher frequency. Current research efforts are expanding to ultra-wide bandgap semiconductors such as gallium oxide Ga2O3). The principal goal of this dissertation is to obtain high quality β-Ga2O3 films with controlled conductivity by magnetron sputtering deposition. The specific objectives are the following: To grow β-Ga2O3 films on sapphire substrates (section 5.2) and on native β-Ga2O3 by rf sputtering (section 5.3), to produce doped and undoped β-Ga2O3 films (Section 5.4). Additionally, to grow Lu2O3/ Ga2O3 and B2O3/Ga2O3 alloy films on (-2 0 1) UID or Sn-doped Ga2O3 and Al2O3 substrates to tune Ga2O3 original bandgap (Section 5.5). To obtain microstructural, morphological, compositional, and optical data from XRD, AFM, SEM, EDS, and UV-Vis characterization methods for all the experiments mentioned above. From this data, correlate the effects of the varying parameters for the optimization of the films, to use the developed films to fabricate Schottky barrier diodes and proceed with the electrical characterization of the fabricated devices (section 5.6).

Gallium Oxide (Ga2O3) is an ultra-wide bandgap semiconductor with a bandgap of 4.5–4.9 eV, which is larger than that of Silicon (Si), Silicon Carbide (SiC), and Gallium Nitride (GaN). A benefit of this ultra-wide bandgap is the high-temperature stability due to the low intrinsic carrier concentration. Another benefit is the high critical electric field (Ec), which is estimated to be from 6 MV/cm to 8 MV/cm in Ga2O3. This allows for a superior Baliga's figure of merit (BFOM) of unipolar Ga2O3 power devices, i.e., they potentially can achieve a smaller specific on-resistance (RON,SP) as compared to the Si, SiC, and GaN devices with the same breakdown voltage (BV). The above prospects make Ga2O3 devices the promising candidates for next-generation power electronics. This dissertation explores the design, fabrication, characterization, and packaging of vertical β-Ga2O3 Schottky barrier diodes (SBDs) and P-N diodes. The power SBDs allow for a small forward voltage and a fast switching speed; thus, it is ubiquitously utilized in power electronics systems. Meanwhile, the Ga2O3 power P-N diodes have the benefit of smaller leakage current, and the diode structure could be a building block for many advanced diodes and transistors. Hence, the study of Ga2O3 Schottky and P-N diodes is expected to provide the foundation for developing a series of Ga2O3 power devices. Firstly, vertical Ga2O3 Schottky and P-N diodes with a novel edge termination (ET), the multi-layer Nickel Oxide (NiO) junction termination extension (JTE), are fabricated on Ga2O3 substrates. This multi-JTE NiO structure decreases the peak electric field (Epeak) at the triple point of device edge when the Ga2O3 diodes are reversely biased. For SBDs, BV reach 2.5 kV, the 1-D junction field reaches 3.08 MV/cm, and the BFOM exceeds 1 GW/cm2. For P-N diodes, BV reaches 3.3 kV, the junction field reaches 4.2 MV/cm, and the BFOM reaches 2.6 GW/cm2. These results are among the highest in Ga2O3 power devices and are comparable to the state-of-the-art vertical GaN Schottky and P-N diodes. Notably, all these diodes are small-area devices. Secondly, large-area (3 mm×3 mm anode size) Ga2O3 Schottky and P-N diodes with high current capability are fabricated to explore the packaging, thermal management, and switching characteristics of Ga2O3 diodes. The same ET is applied for the large-area P-N diode. The fabricated large-area P-N diodes have a turn-on voltage of 2 V, a differential on-resistance (Ron) of 0.2 Ω, and they can reach at least 15 A when measured in the pulse mode. The BV of large-area Ga2O3 P-N diodes varies due to the fabrication non-uniformity, but the best device achieves a BV of 1.6 kV, standing among the highest values reported for large-area Ga2O3 diodes. Also, the large-area Ga2O3 SBDs with similar current rating but with a FP ET are fabricated mainly for the packaging and thermal management studies. Thirdly, medium-area Ga2O3 P-N diodes with a current over 1 A and a higher yield of BV are fabricated to evaluate the JTE's capacitance and switching characteristics. The JTE accounts for only ~11% of the junction capacitance of this 1 A diode, and the percentage is expected to be even smaller for higher-current diodes. The turn-on/off speed and reverse recovery time of the diode are comparable to commercial SiC Schottky barrier diodes under the on-wafer switching test. These results show the viability of NiO JTE for enabling a fast switching speed in high-voltage Ga2O3 power devices. Fourthly, the fabricated large-area Ga2O3 diodes are packaged using silver sintering as the die attach. The sintered silver joint has higher thermal conductivity (kT) and better reliability as compared to the solder joint. Due to the low kT of Ga2O3 material, junction-side-cooled (JSC) packaging configuration is necessary for Ga2O3 devices. For the packaged device, its junction-to-case thermal resistance (RθJC) is measured in the bottom-side-cooled (BSC) and junction-side-cooled (JSC) configuration by the transient dual interface method according to the JEDEC 51-14 standard. The RθJC of the junction- and bottom-cooled Ga2O3 SBD is measured to be 0.5 K/W and 1.43 K/W, respectively. The former RθJC is lower than that of similarly-rated commercial SiC SBDs. This manifests the significance of JSC packaging for the thermal management of Ga2O3 devices. Fifthly, to evaluate the electrothermal robustness of the packaged Ga2O3 devices, the surge current capability of JSC packaged Ga2O3 SBDs are measured. The Ga2O3 SBDs with proper packaging show high surge current capabilities. The double-side-cooled (DSC) large-area Ga2O3 SBDs can sustain a peak surge current over 60 A, with a ratio between the peak surge current and the rated current superior to that of similarly-rated commercial SiC SBDs. These results show the excellent ruggedness of Ga2O3 power devices. Finally, a Ga2O3 integrated diode module consisting of four single-diode sub-modules is designed and fabricated. For many power electronics applications, high current is desired; however, for emerging semiconductors, the current upscaling is difficult by directly increasing the device area because of the limitation of heat extraction capability and the limited material/processing yield. Here we explore the paralleling of multiple Ga2O3 P-N diodes to increase the current level. For each sub-module, the JSC packaging structure is used for heat extraction, and a metal post is sintered to the anode for electric field (E-field) management. RθJC is measured to be 1 W/K for each sub-module. On-board double-pulsed test is performed for both the sub-module and the full module. The sub-module and full module demonstrate 400 V, 10 A and 150 V, 70 A switching capabilities, respectively. This is the first demonstration of Ga2O3 power module and shows a promising approach to upscale of the power level of Ga2O3 power electronics. In addition to Ga2O3 device study, a research is conducted to explore the chip size (Achip) minimization for wide-bandgap (WBG) and ultra-wide bandgap (UWBG) power devices. Achip optimization is particularly critical for WBG and UWBG power devices and modules due to the high material cost. This work presents a new, holistic, electrothermal approach to optimize Achip for a given set of target specifications including BV, conduction current (I0), and switching frequency (f). The conduction and switching losses of the device are considered, as well as the heat dissipation in the chip and its package. For a given BV and I0, the optimal Achip, Wdr, and Ndr show strong dependence on f and thermal management. Our approach offers more accurate cost analysis and design guidelines for power modules. In summary, this dissertation covers the design, fabrication, characterization, and packaging of Ga2O3 Schottky and P-N diodes, with the aim to advance Ga2O3 devices to power electronics applications. This dissertation addresses many knowledge gaps on Ga2O3 devices, including the voltage upscaling (ET), current upscaling (large-area device fabrication, packaging, and thermal management), and their concurrence (module demonstration), as well as the circuit-level switching characterizations.

With electrification progressing across many sectors including industry, automotive and aerospace, the power density requirements are changing. The increased power density results in higher and higher ambient temperatures that electronics are exposed to. The response has been to move towards wide bandgap (WBG) semiconductor devices that can withstand much greater temperatures and can operate at much higher voltages than silicon. Additionally, these WBG devices deliver low drain-source on resistance (RDS_on) capabilities, enabling high current power modules that increase power density even further. This also requires the packaging to evolve in order to withstand the new requirements. As a result, researchers are looking beyond the traditional solder materials for die attach towards options more suited for high temperatures. These reliability-critical die attach applications provide an excellent opportunity to use silver, which has traditionally been held back by its high cost. Silver has a high melting point of 961 ℃, but fine particles of it, in sub-micro or -nano range, can be sintered at a temperature significantly below the melting point. This sintered silver forms a continuous network of silver that has a melting temperature approaching that of bulk silver. While this high melting temperature implies great potential, its actual reliability at those elevated temperatures is not entirely understood. This study aims to advance the implementation of sintered silver in electronic packages by investigating the reliability of sintered silver die attach at elevated temperature, under static and dynamic stressing conditions. First, the degradation at high temperatures is tested by high temperature storage tests. Two different bonded substrates result in different degradation rates in air. CuMo, which is tested in addition to copper as a CTE-matched packaging material to SiC, show slightly greater degradation in air than Cu, especially above 175 ℃ temperature, but in both cases the degradation was significantly reduced by removing oxygen particles from the air. In order to test the reliability under dynamic conditions, a four-point bend setup was built that allowed for time-efficient reliability testing. This allowed for testing at repeated mechanical loading conditions, as well as allowing for a time-efficient method of fatigue testing than traditional thermal cycling. The setup was used to test board-level sintered silver die attach samples for multiple applied mechanical strains and thermal conditions, allowing for an empirical relationship to be developed. The correlation can provide a critical design tool for design engineers to predict reliability depending on mechanical and thermal conditions. To demonstrate the translatability of the mechanical cycling test to a thermal cycling scenario, a finite element model was used to relate the experimentally obtained failure times to the strain energy density for each of the test conditions. A correlation was then developed that predicts the reliability based on the strain energy density, regardless of the type of loading, assuming that interfacial crack propagation is the failure mechanism. It was demonstrated that the mechanical test bench can run 900 cycles during the same time period that one cycle can be run in a typical thermal cycling test.

This master's thesis is dedicated to enhancing the reliability of silver sinter die attachments, a pivotal component within the dynamic realm of power electronics. The study is meticulously organized into four distinct chapters, each contributing to a comprehensive understanding of silver sinter die attachment reliability and its implications for contemporary electronic packaging. In Chapter 1, an introduction is provided to the significance of silver sinter die attachment in the context of power electronics, underlining the imperatives associated with miniaturization, weight reduction, and heightened efficiency. The compelling need to investigate die attachment properties, particularly in high-temperature and high-power-density environments, is emphasized. Chapter 2 delves into the intricate design and fabrication of an H-bridge module, offering a practical framework for examining the die attachment process. Chapter 3 undertakes a thorough analysis of the reliability of the silver sinter die attachment layer. Employing Finite Element Analysis (FEA) in Ansys, the behavior of the silver sinter die attachment layer under varying stress scenarios is modeled and comprehensively understood. This in-depth analysis includes a comparative exploration of temperature cycling and power cycling reliability tests, providing valuable insights into the die attachment's response under diverse operational conditions, encompassing the aspects of plasticity through the Anand viscoplasticity model and lifetime modeling. Lastly, in Chapter 4, pioneering research is introduced, aimed at enhancing the mechanical reliability of silver sinter die attachment. This novel approach explores the integration of copper nanowires into the substrate interface, offering a unique strategy to fortify the attachment's mechanical robustness and durability. This work addresses the burgeoning demand for a comprehensive investigation of die attachment reliability, especially in the face of rising power densities and temperatures in power electronics.

Convective heat transfer by jet impingement cooling offers a suitable solution for high heat flux applications. Compared to techniques that rely on bulk conduction in series with convection, direct liquid impingement reduces the thermal resistance between power device hot spots and the coolant. Using additive manufacturing processes, location specific jets can be integrated into high voltage power electronics systems. Custom manifolds can be designed to reduce pressure drop, while simultaneously fine-tuning the thermal management efficiency. Although capable of highly efficient cooling, static impingement devices must be designed for the worst-case cooling requirements for a transient power profile, possibly resulting in wasted hydraulic performance. This work seeks to understand the balance between high performance external jet impingement with internal immersed cooling of high voltage power electronics. With the use of a variable area iris mechanism, high frequency pulsations are introduced into the jet cooling of a base-plate level testbed. This same actuator is then used to analyze the impact on thermal cycling and pressure drop during real-world power profiles. From a thermal packaging perspective, the base plate layer and other insulation features will inherently increase the base line resistance value. Therefore, the second portion of this work is to evaluate the applicability of direct immersion jet impingement cooling using dielectric fluids. In this part, a thermal test vehicle is first built to understand the thermal performance of a single jet of dielectric fluid. Then, this cooling method is imbedded into the housing of a 1.2kV SiC power module to analyze the trade-off between conductive thermal spreading and reduced convective thermal resistance.

In this dissertation, the modeling, design, and control of power electronic converters are conducted for the unbalanced loads and groundings in the microgrid. First, from the system planning perspective, a detailed model for a grid-forming inverter is proposed considering the control impacts for unbalanced power flow analyses. The proposed model is applied for the unbalanced power flow analysis in the IEEE 13-bus and 34-systems. The results demonstrate that the proposed model can achieve a significant increase in the negative sequence (NS) voltage calculation accuracy. Second, a comprehensive analysis of NS current distribution among different grid-forming sources is conducted. The analysis considers different grid-forming source types and control implementations. The analysis is verified through simulation and experimental testing. A NS impedance design approach is proposed to realize the NS current distribution among different grid-forming sources (inverters and generators) in a microgrid with multiple source locations considering the topology impacts. The proposed method is demonstrated through simulation and experimental testing on a converter-based hardware testbed. To verify the proposed approach, a novel synchronous generator emulator is also proposed considering the unbalanced load impacts. Third, to deal with the potential loss of grounding in the islanded microgrid, two novel grounding schemes are proposed, which are an inverter-based grounding scheme and a controllable DER transformer-based grounding scheme. Simulation and experimental demonstration of two grounding schemes are also conducted. Then, the unbalanced load impacts on the power conditioning system (PCS) for a transformer-less asynchronous microgrid are analyzed. The PCS utilizes the modular multi-level converter (MMC) topology. Based on the analyses, the design and control solutions for the MMC are proposed and demonstrated on an actual 10 kV SiC MOSFET-based MMC up to 25 kV dc-link voltage. Moreover, the unbalanced load impacts on DER’s interfacing converter are analyzed. Based on the DER’s ripple capability, the control strategy is proposed for the dc/dc stage to eliminate or partially support the second-order frequency current from the unbalanced load. The design of the dc-link capacitors is also conducted. The dc-link capacitor design and the proposed control algorithms are verified through simulation and experimental testing.

With the growth of electric vehicle (EV) popularity, different charging options to increase user convenience and reduce charging time such as high power wireless charging are increasingly being developed and researched. Inductive wireless power transfer (WPT) systems for EVs must meet specifications such as stray field, battery power and voltage operating range, efficiency, and ground clearance. The coil geometry and design have a large impact in meeting these constraints. Typical design approaches include iterative analysis of predetermined coil geometries to identify candidates that meet these constraints. This work instead directly generates WPT coil shapes and magnetic fields to meet specifications and constraints through the optimization of Fourier basis function coefficients and that can be used to predict system efficiency and performance. The proposed Fourier Analysis Method (FAM) applies to arbitrary planar coil geometries and does not rely on iterative finite-element analysis (FEA) simulations. This flexibility allows for rapid design evaluation across a larger range of coil geometries and specifications. The method is used to consider the trade-off of coil current and stray field for given power levels to illustrate the flexibility and generality of the method. A 6.6 kW proof-of-concept demonstrator WPT system is built from the optimization result to compare model efficiency, stray fields, and performance to experimental measurements. The methodology is then used in the optimization, design, analysis, and testing of two 120 kW demonstrators, including thermal modeling and integration.

Abstract: Nowadays, among renewable energy sources, PV systems are highly popular due to their easy installation and affordability. A key component of the PV system is the inverter, which can significantly affect the reliability, efficiency, and power quality of the system. The PV inverters are required to track the maximum power point (MPP) of the panel to maximize the production of the system. To achieve this goal, the inverter must be able to generate the required output waveforms for a wide range of input voltages. Normally, two-stage inverters are used to achieve this goal and produce high-quality output power; however, both stages process the full output power and have a high number of reactive components with high switching stress which can result in lower power density and higher losses of the converter. In this thesis, new topologies are proposed to reduce the required number of passive components for the inverter while allowing it to operate for a wide range of input voltages and maintain the power quality of the output. The first proposed design features an extended input voltage range using a cascaded full-bridge inverter with a cascaded floating capacitor, leveraging low-frequency operation to generate fundamental output voltage components. It is coupled with low-voltage high-frequency operation to mitigate harmonics. A comprehensive control mechanism is used to regulate the modulation angle of the low-frequency full bridge. Additionally, a synchronous (or DQ) reference frame controller is used to regulate current and enable MPP tracking. To further reduce the blocking voltage of the capacitor-connected full bridge, the second structure replaces the PV-connected full bridge with a T-type inverter, halving the blocking voltage. The flyback-assisted inverter is also proposed to further extend the inverter's operating input voltage range. This topology integrates cascaded full-bridge inverters with a flyback converter. This configuration allows the high-frequency full bridge to process a portion of the power based on input voltage. Precise control mechanisms for determining modulation angles and maximum power point tracking (MPP) in PV systems are implemented. Furthermore, the controller deactivates the flyback converter when the photovoltaic (PV) voltage reaches an optimal level for generating the desired output voltage. This reduces switching losses and can further improve converter efficiency. Furthermore, a cascaded full-bridge converter with a single switching frequency is proposed to accommodate the broad voltage range of the flyback-assisted converter, while minimizing component count, and improving power density. A new control structure for the fast and robust operation of the inverter is proposed. These control mechanisms can independently regulate the power of each full bridge, allowing the converter to operate within a wide range of input voltages.

The aviation industry faces a growing imperative to decrease greenhouse gas emissions and transition towards more electric aircraft (MEA) and all-electric aircraft (AEA). One key requirement for a successful transition is increasing the power density and efficiency of onboard power converters. Wide-bandgap (WBG) power switching devices, such as silicon carbide (SiC), present a promising solution due to their high voltage capability and rapid switching speed. However, these devices also pose a challenge as their fast switching speed can adversely affect insulation systems. This dissertation aims to investigate and offer a deeper understanding of, as well as solutions to, the challenges related to partial discharge (PD) in aircraft power wiring under high dv/dt voltage pulses generated by SiC devices.The dissertation begins with an overview of the significant technical challenges related to PD that arise from using SiC device-based variable speed drives (VSD). It then discusses existing studies addressing these challenges and the failure of insulation systems due to PD. The literature review highlights disagreements in current research and the absence of comprehensive investigations into PD behavior caused by high dv/dt square-wave voltage pulses and their impact on the premature failure of insulation systems.Subsequently, the dissertation delves into the challenges associated with the PD phenomenon in aviation wires, explaining the factors that influence PD behavior, accurate PD detection methods, and the extraction of meaningful features to quantify PD intensity. This is followed by an experimental study of PD-induced aging under various conditions to explore the effects of different variables on PD behavior and the failure mechanism of aviation wires. The experimental conditions are chosen to examine voltage rise time, voltage amplitude, ambient pressure, ambient temperature, and the dielectric material of aviation wires.The experimental results reveal the complexity of PD behavior and the associated degradation process, highlighting the need for artificial intelligence (AI) and machine learning (ML) to interpret and predict insulation status. The dissertation then presents the implementation of ML, showcasing feature extraction, data preparation, model training, and the successful prediction of remaining service life. Finally, the dissertation concludes with a summary of key findings and recommendations for future research.

Power device robustness refers to the device capability of withstanding abnormal events in power electronics applications, which is one of the key device capabilities that are desired in numerous applications. While the current robustness test methods and qualification standards are developed across the 70 years of Silicon (Si) device history, their applicability to the recent wide bandgap (WBG) power devices is questionable. While the market of WBG power devices has exceeded $1 billion and is fast growing, there are many knowledge gaps regarding their robustness, including the failure or degradation physics, testing methods, and lifetime extraction. This dissertation work studies the robustness of Gallium Nitride (GaN) power device. The structures of many GaN power devices are fundamentally different from Si or Silicon Carbide (SiC) power devices, leading to numerous open questions on GaN power device robustness. Based on the device structure, this dissertation is divided into two parts: The first half discusses the robustness of lateral GaN high electron mobility transistor (HEMT), which recently sees rapid adoption among wide range of applications such as the power adapter and chargers, data center, and photovoltaic panels. The absence of p-n junction between the source and drain of GaN HEMT results in the lack of avalanche mechanism. This raises a concern on the device capability of withstanding surge-energy or overvoltage stress, which hinders the penetration of GaN HEMTs in broader applications. To address this concern, the study begins with conducting the single-event unclamped inductive switching (UIS) test on two mainstream commercial p-gate GaN HEMTs with the Ohmic- and Schottky-type gate contacts, where the GaN HEMT is found to withstand surge energy through a resonant energy transfer between the device capacitance and the loop inductance. The failure mechanism is identified to be a pure electrical breakdown determined by device transient breakdown voltage (BV). The BV of GaN HEMT is further found to be "dynamic" from the switching tests with various pulse widths and frequencies, which is further explained by the time-dependent buffer trapping. This dynamic BV (BVDYN) phenomenon indicates that the static or single-pulse test may not reveal the true BV of GaN HEMT in high frequency switching applications. To address this gap, a novel testbed based on a zero-voltage-switching converter with an active clamping circuit is developed to enable the stable switching with kilovolt overvoltage and megahertz frequency. The overvoltage failure boundaries and failure mechanisms of four commercial p-gate GaN HEMTs from multiple vendors are explored. In addition to the frequency-dependent BVDYN, two new failure mechanisms are observed in some devices, which are attributable to the serious carrier trapping in GaN HEMTs under the high-frequency overvoltage switching. At last, based on the findings in the high frequency overvoltage test (HFOT), a physics-based lifetime model for commercial GaN HEMTs utilizing the device on resistance (RON) shift is established and validated by experimental results. Overall, the switching-based test methodology and experimental results provide critical references for the overvoltage protection and qualification of GaN power HEMTs. The second half of the dissertation discusses the robustness of the vertical GaN fin-channel junction field effect transistor (Fin-JFET), a promising pre-commercialized GaN power device with the p-n junction embedded between the gate and drain which enables the avalanche breakdown. The robustness study on GaN JFET follows similar test approaches as Si metal-oxide-semiconductor field-effect transistor (MOSFET) with two key interests: the avalanche and short circuit capabilities. The avalanche breakdown is first explored via the single-event and repetitive UIS tests and under various gate drivers, from which an interesting "avalanche-through-fin-channel" mechanism is discovered. By leveraging this avalanche path, the electro-thermal stress migrates from the main blocking p-n junction to the n-GaN fin channel, resulting in a very favorable failure-to-open-circuit signature. The single-pulse critical avalanche energy density (EAVA) of vertical GaN Fin-JFET is measured to be as high as 10 J/cm2, which is much higher than the Si MOSFET and comparable to the SiC MOSFET. The short circuit capability is explored utilizing the hard-switching fault on the 650-V rated GaN Fin-JFET, with a gate driving circuit identical to the switching application to best mimic device operation in converters. The short circuit withstanding time is measured to be 30.5 µs at an input voltage of 400 V, 17.0 µs at 600 V, and 11.6 µs at 800 V, all among the longest reported for 600-700 V normally-off transistors. In addition, the failure-to-open-circuit signature is also shown in the single-event and repetitive short circuit tests; all devices retain the avalanche breakdown after failure, which is highly desirable for system applications. These results suggest that, while GaN HEMT is already available in market, vertical GaN Fin-JFET shows superior avalanche and short-circuit robustness and thereby can unlock great potential of GaN devices for applications like automotive powertrains, motor drives, and grids.

Power electronics plays an important role in many energy conversion applications in modern society including consumer electronics, data centers, electric vehicles, and power grids, etc. The key components of power electronic circuits are power semiconductor devices including diodes and transistors, which determine the performance of power electronics circuits. Traditional power devices are based on the semiconductor silicon (Si), which have already reached the silicon's material limit. Gallium nitride (GaN) is a wide bandgap semiconductor with high electron mobility and high critical electric field. GaN-based power devices promise superior device performance over the Si-based counterpart. The primary design target of a unipolar power device is to achieve low on-resistance and high breakdown voltage. Although GaN high electron mobility transistor (HEMT) is commercially available in a voltage class from 15 V to 900 V, the performance of GaN devices is still far below the GaN material limit, due to several reasons: 1) To achieve the normally-off operation in a GaN HEMT, the density of two-dimensional electron gas (2DEG) channel cannot be too high; this limits the on-resistance reduction in the access region. 2) The gate capacitance of GaN HEMT is usually low so that the carrier concentration in the channel underneath the gate is relatively low, limiting the on-resistance reduction in the gated channel region. 3) The electric-field distribution in the drift region is not uniform, resulting in a limited breakdown voltage. We proposed to use the junction-based structure in GaN power devices to address the above problems and fully exploit GaN's material properties. The first part of this dissertation characterizes nickel oxide (NiO) as a p-type material to construct the junction-based GaN power devices. Although the homogenous p-GaN/n-GaN junction is preferred in many devices, the selective-area, p-GaN regrowth can lead to excessive leakage current; in comparison, the p-NiO/n-GaN junction is stable without leakage. This section describes the optimization of NiO deposition as well as the NiO characterization. Although acceptor in NiO is not generated by impurity doping, the acceptor concentration modulation is realized by tuning the O2 partial pressure during the sputtering process. Practical breakdown electric field is also characterized and confirmed to be higher than GaN. These results provide the design guidelines for NiO-GaN junction-based power devices. The second part of this dissertation demonstrates the 3D NiO-GaN junction gate to improve the GaN HEMT's on-resistance. The 3D junction gate structure enables a high carrier concentration under the gate region in the device on-state. Meanwhile, the strong depletion effect of the junction-based gate allows for a robust normally-off operation; as a result, the GaN wafer with a higher 2DEG concentration can be used to achieve both normally-off and low on-state resistance in HEMT devices. Simulation is also performed to project the performance space of trigate GaN junction HEMTs using the p-GaN instead of NiO. The third part of this dissertation presents the application of the p-GaN/n-GaN junction in the drift region of the multi-channel lateral devices to achieve the high breakdown voltage. Here p-GaN is grown in-situ with the multi-channel AlGaN/GaN structure, and there is no leakage problem. The structure is designed to achieve charge balance between the acceptor in p-GaN and the net donor in the multichannel AlGaN/GaN. This design enables a uniform electric field distribution and breakdown voltage over 10 kV. The fourth part of this dissertation presents the application of the p-NiO/n-GaN junction in vertical superjunction (SJ) devices. We show the design and simulation of this heterojunction structure in a SJ and confirm the uniform electric field and high breakdown voltage under the charge balance. Then the device fabrication is presented in detail, which mainly comprises the deep GaN trench etch, NiO self-aligned lift off, and photoresist trench planarization. The optimized device shows a trade-off between its drift region specific on-resistance versus breakdown that exceeds the 1D GaN's limit. The last part of this dissertation is exploring the design and fabrication of p-GaN/n-GaN based SJ devices. First, the challenges in p-GaN regrowth especially the introduction of interface impurities are discussed, followed by device simulation and modeling to optimize the SJ performance considering these interface impurities. The activation of regrown p-GaN in deep trenches is more difficult than planar p-GaN, and we present the characterization and physical model for the activation of the deep buried p-GaN. Last, the results of p-GaN filling regrowth and the acceptor concentration calibration in the lightly doped p-GaN are presented and discussed. In summary, our work combines experimental device fabrication and characterization, TCAD simulation, and device modeling to demonstrate the benefit of multi-dimensional, junction-based GaN power devices as compared to the traditional GaN power devices. The junction-based structure at gate region can provides stable normally-off operation and low on-resistance. When being applied to the drift region, the multidimensional junction structure can push the device specific on-resistance versus breakdown voltage trade-off near or even exceeding the material limit. These results will advance the performance and application spaces of GaN power devices.

Power electronics are heavily involved in power and energy systems in plenty of applications nowadays. The increase of demand brings more challenges into simulations for development. Considering the complexity of the systems and high frequency operational conditions, this paper presents comprehensive research on modeling, simulating, and validation on ground vehicle propulsion system applications. To reduce the computational burden, the Power Electronics Building Blocks concept is utilized to simplify the structure of modeling under different conversion scenarios in ground vehicle systems. In addition, the Average and Switching versions models are included. To speedup the simulation, the engagement of advanced computing technique in simulations are introduced to realize faster-than-real-time simulations. By the comparison between widely used slower-than-real-time simulations in academy and faster-than-real-time simulation with advanced computational technology, the improvements are presented. Other than engaging advanced technique, this paper proposed an advanced model method different from the Average and Switch method but the combination with the advantages of accuracy and fast simulation time. Furthermore, to verify all the modeling and simulation results proposed, a hardware design is presented, and the results validation are provided at the end.

DC bus capacitor voltage unbalance in Neutral Point Clamped (NPC) multilevel inverters is an inherent challenge with a severe effect on five and higher-level inverters. Capacitor voltages unbalance depends on type of inverter loading and modulation techniques. Following this, modulation-based (soft) voltage balancing schemes manipulate modulations in accordance to load current conditions, while hardware-based (active) balancing, introduce external circuitry dedicated for voltage balancing. Current soft balancing schemes and modulations with unbalance mitigation for five-level NPC inverters require a high number of switchings, especially at high modulation index operations. Moreover, active balancing techniques come with high components count. This dissertation presents, three parts modulation and hybrid voltage balancing scheme, novel solutions for five-level NPC inverters to address limitations seen in earlier voltage balancing solutions. When implemented together, these solutions offer low switching operation and reduce voltage balancing circuitry.The three parts modulation combines three sub-modulations, which switch into different number of DC links within a switching period. These sub-modulations activate at different reference signal magnitude ranges. Three parts modulation reduces voltage unbalance in comparison to conventional modulation while offering soft balancing opportunities. Furthermore, the modulation offers operation with reduced switching when compared to state of the art carrier-based modulations suited for voltage balancing. To address voltage unbalance associated with the modulation, hybrid balancing scheme is preferred as it maintains inverter operation with low switching characteristics. These behaviors are analytically characterized, and verified using Matlab/SIMULINK simulations and experimental testing for both single-phase and three-phase inverters.The hybrid balancing uses active balancing and soft balancing techniques working together to balance DC bus capacitor voltages. Following this, hybrid balancing requires suitable modulation technique, which offer sufficient opportunity for soft balancing. This requirement is met by three parts modulation, which enables successful hybrid balancing over wide operational conditions with reduced switching characteristics. Furthermore, hybrid balancing achieves reduced components count due to flyback balancing circuit implementation and balancing load sharing with soft balancing. Voltage balancing analysis over critical range of modulation index demonstrates hybrid voltage balancing capability by identifying operational regions of the component balancing techniques. This is justified through Matlab simulation and verified with experimental testing under different modulation and load conditions.Circuit analysis of the five-level DC bus and a voltage unbalance model provide insights how the systems react as a plant and to balancing current inputs. In addition to this, discussion of control efforts identifies system nonlinearities that limit plant model utilization. Following this, hybrid balancing explores control designs independent of system plant model, where a unique integrated control strategy is designed to meet the needs of hybrid balancing control. Experimental tests verify performance of the integrated control strategy under operational setup with high voltage unbalance.

GaN holds significant potential as a material for vertical p-n diodes, enabling the realization of devices with reverse breakdown voltages of 5 kV or higher. Carbon serves as the primary compensating dopant in the growth process, incorporated into GaN during metalorganic chemical vapor deposition (MOCVD) growth. The level of carbon incorporation depends on several factors, including growth rate, ammonia flow, temperature, pressure, and trimethylgallium (TMGa) flow. Through guided empirical modeling, it was demonstrated that the carbon incorporation in GaN growth could be predicted using a single parameter based on the ratio of ammonia flow to the growth rate. This model accurately predicts carbon concentrations ranging from 1x1017 to 5x1014 cm-3 while allowing for maximized growth rates. Other extrinsic dopants have either been reduced below the threshold of consideration or modeled using similar single-parameter relationships. By identifying the dominant extrinsic dopants and accounting for them, an intrinsic defect with a concentration of 2.2x1015 cm-3 was identified. By combining these relationships, growth conditions for n-GaN were optimized, resulting in electron concentrations as low as 1x1015 cm-3. Leveraging these techniques, p-n diodes were grown, achieving a reverse breakdown voltage as high as 3.1 kV.

Power electronic systems and components that can operate in environments with ambient temperatures exceeding 250 °C are needed for innovation in automotive, aerospace, and down-hole applications. With the imminent mass electrification of transportation and industry, the high-temperature electronics market value is anticipated to grow to $15 billion by the end of 2023. Conventionally, silicon (Si)-based converters are used in these applications; however, as operating temperatures continue to increase, the inherent limits of these systems are being met. The primary limitations for the high-temperature operation of semiconductor devices is the intrinsic carrier concentration, dictated primarily by the bandgap of the material, which increases with temperature. Wide-bandgap (WBG) power semiconductors, primarily silicon carbide (SiC) and gallium nitride (GaN), have been adopted for use in these applications, but exhibit a degradation in performance at elevated temperatures. As such, gallium oxide (Ga2O3), an ultrawide-bandgap (UWBG) material with controllable doping and the potential for inexpensive substrates, has presented itself as a potential contender for use in high-temperature power electronics applications. The UWBG of Ga2O3, 4.8 eV compared to 1.1 eV for Si, 3.2 eV for SiC, and 3.4 eV for GaN, allows it to achieve nearly 1033 lower intrinsic carrier concentration than Si, permitting Ga2O3 power devices to theoretically operate at significantly higher temperatures. In addition, unipolar Ga2O3 devices have a better theoretical limit with respect to the relationship between on-resistance and breakdown voltage, which could enable higher power density and power conversion efficiency. While Ga2O3 exhibits potential in these regards, its low thermal conductivity (11–27.0 W/m·K compared to 148 W/m·K for Si, 350 W/m·K for SiC, and 130 W/m·K) means that standard packaging and cooling techniques are not suitable or effective. Furthermore, conventional polymeric and organic encapsulant materials are typically limited to operating temperatures of 200 °C and novel materials must be evaluated. This work outlines and evaluates an electro-thermal device-package co-design modeling platform that can be utilized for the efficient and accurate modeling of Ga2O3 devices and their associated packaging, with the goal of overcoming the challenges of the low thermal conductivity of Ga2O3. This permits for the electrical and thermal performance of the devices and the package to be designed in tandem for an effective design. Next, six high-temperature encapsulation materials are evaluated and conclusions are drawn about each material's feasibility for use as a dielectric encapsulation material for a power module operating at temperatures exceeding 250 °C. This simulation platform and material analysis was then used to design and fabricate a 300 °C, 1.2 kV half-bridge power module utilizing Ga2O3 diodes to assess thermal and electrical performance.

Abstract: In the wake of increasing demand for DC-DC converters with high power density and high efficiency, the design of modern power converters has evolved into a multi-objective optimization problem with multiple uncertainties associated with parameter and component selection. The iterative design procedure, manual component selection, and the diverse nature of passive and active components complicate optimum DC-DC converter design and comparison. Existing methods suffer from excessive computation time, inaccurate component modeling, and inadequate design variables, resulting in sub-optimal solutions. In this thesis, the design of a non-isolated DC-DC power converter is formulated as a multi-objective optimization problem, which seeks to reduce the total converter volume and power loss. A new component modeling method is proposed, that incorporates the impact of major converter components, including the inductor, capacitor, MOSFET, and heat sink, to overcome the uphill challenge of automating the optimization process. This model allows for the mathematical expression of design objectives in terms of technology-specific parameters and converter operating conditions without selecting or assuming specific components. After the optimal solutions are determined, all components can be selected in one step at the end of the process. Experimental and data-driven analyses are conducted to confirm the validity of the component modeling and design method. The automated optimum design procedure is then used to study the effects of various parameters on design objectives and to compare the efficiency and power density of different converter topologies for particular applications.

Abstract: The linear control structure shows limited bandwidth for high-performance ac drive applications and also it is difficult to deal with complex systems with multi-objective optimization demand and nonlinear, high-order characteristics. With the development of more powerful digital platforms and the emergence of new switching devices, the control algorithm for industrial drives application is constantly evolving and significant research efforts have been carried out over the past several years. Particularly, model predictive control (MPC) emerges as an attractive solution to power converters and it has become a research hotspot recently. The time-domain modeling process makes MPC naturally suit the multiple-input multiple-output (MIMO) systems and it shows obvious advantages in the field of power electronics such as the intuitive concept, faster dynamic response, multi-variable control capability, nonlinear objective handling ability, etc. The research presented in this thesis thus exploits the benefits provided by MPC to address the prominent control challenges existing in industrial motors driven by current-source converters (CSCs) and voltage source converters (VSCs). Particularly, the medium voltage (MV) CSCs are applied with the megawatt power range such as in the wind tunnel drive system, fans and compressors, etc. While the VSCs can be more frequently seen in the relatively lower power occasion, such as electric vehicles, where the switching frequency can be higher to hundreds of kilohertz. The control scheme of both CSCs and VSCs should meet the increased demand and requirements imposed by industrial drive applications because these are directly related to whether the motor can work normally, and also the system stability, reliability, efficiency, robustness, etc. Considering the limitation of the conventional linear approach and the lack of MPC design for the high-order system and back-to-back(BTB) drive-level optimization, the main work in this thesis can be divided into the following three aspects. Firstly, the flexible cost-function design mode provided by MPC is exploited to coordinately control the BTB structure, achieving system-level optimization compared to the conventional linear approach. For the BTB CSCs-fed drives, the proposed cost function with direct multi-variable feedback is developed to solve the filter resonance with the second-order characteristic. Besides, the robustness is enhanced by incorporating the disturbance observer, and the long horizon prediction case with the benefits of only line current feedback is presented for such a second-order system. Furthermore, the selective harmonic magnitude penalization is included in the cost function to reject the grid-side harmonic. According to the operated speed region of the motor, the peak-to-peak value of the common mode voltage (CMV) and its third-order harmonic are respectively suppressed to address the common mode (CM) resonance for the transformerless operation. On the other hand, regarding the VSCs-fed drives for relatively low power applications, the nonlinear control objective in terms of intermediate dc-link capacitor current ripple reduction is developed in the BTB structure, which contributes to the lifetime extension or the size reduction of the dc-link capacitor. Secondly, the potential of MPC is fully developed to control multiple state variables in the third-order LCL-filtered system, avoiding the nested multi-loop control structure in the linear approach. This benefit can be seen in both the LCL-filtered grid-connected application and the long cable-fed motor side with an output LC filter. The proposed MPC schemes show significant benefits in terms of the intuitive design concept, faster dynamic response, and simplified tuning procedure compared to the conventional multi-loop approach. Finally, when applying the MPC to the power converters with high switching frequency operation, the high sampling/interrupt frequency demand becomes a great challenge because of the big computational difficulty. Therefore, the multi-rate technique is designed into the MPC formulation, where the switching frequency can be significantly increased and a low sampling/interrupt frequency can be adopted. In this case, the quite long interrupt period allows the easy realization of the control algorithm and an abundant computational margin can remain in the digital platform. The proposed multi-rate MPC by enabling longer interrupt duration is more efficient than the conventional way focusing on how to reduce the execution time of the MPC algorithm itself. The multi-rate MPC also stands for a general formulation of MPC in the field of power electronics.

Wide bandgap (WBG) semiconductor devices are becoming increasing popular in power electronics applications. However, WBG semiconductor devices generate a substantial amount of conducted electromagnetic interference (EMI) compared to silicon (Si) devices due to their ability to operate at higher switching frequencies, higher operating voltages and faster slew rates. This thesis explores and analyzes EMI mitigation techniques that can be applied to a power module architecture at the packaging level. In this thesis, the EMI footprint of four different module architectures is measured experimentally. A time domain LTspice simulation model of the experimental test setup is then built. The common mode (CM) EMI emissions that escape the baseplate of the module into the converter is then examined through the simulation. The simulation is used to explore the CM noise footprint of eight additional module architectures that were found in literature. The EMI trends and the underlying mitigation principle for the twelve modules is explained by highlighting key differences in the architectures using common mode equivalent modelling and substitution and superposition theorem. The work aims to help future module designers by not only comparing the EMI performance of the majority of module architectures available in literature but by also providing an analysis methodology that can be used to understand the EMI behavior of any new module architecture that has not been discussed. Although silicon carbide (SiC) modules are used for this study, the results are applicable for any WBG device.

Direct current (DC) distribution system has shown potential over the alternative current (AC) distribution system in some application scenarios, e.g., electrified transportation, renewable energy, data center, etc. Because of the fast response speed, DC solid-state circuit breaker (SSCB) becomes a promising technology for the future power electronics intensive DC energy system with fault-tolerant capability. First, a thorough literature survey is performed to review the DC-SSCB technology. The key components for DC-SSCB, including power semiconductors, topologies, energy absorption units, and fault detection circuits, are studied. It is observed that the prior studies mainly focus on the basic interruption capability of the DC-SSCB. There are not so many studies on SSCB’s size optimization or system-friendly functions. Second, an insulated gate bipolar transistor (IGBT) based lightweight SSCB is proposed. With the reduced gate voltage, the proposed SSCB can limit the peak fault current without the bulky and heavy fault current limiting the inductor, which exists in the conventional SSCB circuit. Thus, the specific power density of the SSCB is substantially improved compared with the conventional design. Meanwhile, to understand the impact of different design parameters on the performance of SSCB, an analytical model is built to establish the relationship between SSCB dynamic performance and operating conditions considering the key components and circuit parasitics. Simulation and test results demonstrate the accuracy of the proposed model. To limit the fault current with the proposed SSCB without a current limiting inductor, power semiconductors need to operate in the active region temporarily. During this interval, a severe voltage oscillation has been observed experimentally, leading to the DC-SSCB overstress and eventually the failure. A detailed MATLAB/Simulink model is built to understand the mechanism causing the voltage oscillation. Three suppression methods using enhanced gate drive circuitry are proposed and compared. Test results based on a 2kV/1kA SSCB prototype demonstrate the effectiveness of the proposed oscillation mitigation method and the accuracy of the derived model. Meanwhile, when the system fault impedance is close to zero (e.g., high di/dt), the influence of the parasitic inductance contributed by interconnection (e.g., bus bar, module package, etc.) cannot be neglected. To study the influence of the bus bar connections on SSCB with high di/dt, a Q3D extractor is adopted to extract the parasitic parameters of the SSCB and understand the influence of different bus bar connections. A vertical bus bar is proposed to suppress the side effect and verified by the Q3D extractor and experimental results. Finally, a system-friendly SSCB is demonstrated. The proposed gate drive enables the SSCB to operate in the current limitation mode for the overcurrent limitation. The current limitation level and limitation time can be tuned by the gate drive. Then, this dissertation provides an all-in-one solution with integrated circuitries as the fault detector, actuator for the semiconductor’s operating status regulation, and coordinated control. This allows the developed SSCB to limit system fault current not exceeding short-circuit current rating (SCCR) and also take different responses under different fault cases. The feasibility and the effectiveness of the proposed system-friendly SSCB are validated with experimental results based on a 200V/10A SSCB demonstrator.

This study investigates the threat of hardware Trojans (HTs) in power electronics applications, a rising concern due to the growing demand for cost-effective embedded solutions in power systems. With the supply chain for electronic hardware devices expanding globally, particularly to low-cost foundries in foreign locations, there is an increasing risk of HT attacks. While there has been extensive research on HTs in computer applications, little consideration has been given to their threat in power electronics. This study demonstrates the effectiveness of a power electronics HT by implementing a novel HT design into a gate drive circuit. Additionally, the research proposes several HT designs that exploit factors unique to power circuits, such as high power delivery and analog circuitry in order to illustrate the distinct attack space. The research highlights the need for enhanced detection, protection, and prevention methods in power electronics applications and offers a roadmap for future studies to develop more effective countermeasures and algorithms to mitigate the risks of HT attacks in power electronics.

Power converter topologies are continually evolving and improving especially as new applications such as space exploration mature, and new power architectures emerge. One such evolutionary branch of power converters is hybrid switched-capacitor (SC) converters which leverage capacitors as highly energy-dense components, high figure-of-merit switching devices, and small magnetics to realize high-performance power electronics. To fully exploit the benefits of this relatively new class of power converters requires investigation into control schemes. Whether using conventional switching control strategies or developing novel arrangements, this work explores the theoretical and practical intricacies of applying various switching schemes to hybrid SC converters. Due to the reliance on capacitors for energy processing, SC converters typically suffer from charge-sharing losses when capacitors are charged/discharged into other capacitors or sources. However, adding a small inductance to the circuit and incorporating clever switching patterns can reduce or eliminate these losses. Furthermore, with an increase in the number of switching devices over traditional converters, losses associated with those switches may also increase. This work examines soft-switching techniques and how application to hybrid SC converters differs from previous works. Finally, a hybrid SC converter is designed and tested for low-voltage automotive powertrain applications. In an industry that has strict regulations, this work seeks to demonstrate these new topologies can meet the required specifications and can do so with high performance as well. Switching techniques for mitigation of electromagnetic interference are evaluated against regulated limits and against efficiency performance. Theory, analysis, and experimental results are expounded upon for several switching control strategies of hybrid SC converters addressing challenges of high-efficiency, low-noise, and high-density for applications to data center power delivery, space technology, and automotive powertrains.

III-nitride semiconductors have revolutionized modern electronics by enabling high-power radio-frequency and lighting technologies. These materials hold immense potential for new technologies such as miniaturized displays, ultraviolet sterilization, and fast electric-vehicle charging. However, there are still performance bottlenecks that need to be addressed. In this thesis, I investigate the microscopic mechanisms that limit the performance of nitride semiconductors in power-conversion and lighting applications, and propose new solutions using quantum-mechanical methods that connect the microscale physics to macroscale device phenomena. First, I examine the limitations of III-nitride semiconductors in power-conversion applications. To increase the breakdown voltage of GaN, which is critical for higher power devices, it is promising to alloy it with Al. However, this approach decreases the electron mobility due to alloy scattering. In this thesis, I develop a novel approach to calculate the low-field mobility of semiconductor alloys from first principles. I find that the mobility of AlGaN decreases by a factor of $sim$7 compared to GaN. Consequently, Al compositions above 75% are required to achieve even a two-fold increase in the Baliga Figure of Merit (BFOM) compared to GaN, at which point impurity doping becomes increasingly difficult. To address this issue, I propose using atomically thin superlattices of AlN and GaN that are free of disorder. My calculations indicate that these nanostructures exhibit a 4.8 eV band gap and a mobility $3-4times$ higher than random AlGaN. By accounting for the dopant ionization fraction in the BFOM, I show that the superlattices exhibit the highest modified BFOM among prominent competing semiconductors. Second, I investigate the mechanism that causes InGaN light-emitting diodes (LEDs) to suffer from an emission blueshift and linewidth broadening when operated at high currents, leading to a degradation of their color properties. By systematically considering the effects of polarization-field screening, phase-space filling, and many-body plasma renormalization, I comprehensively explain the current-dependent spectral characteristics of polar III-nitride quantum wells. My analysis overturns the prevailing hypothesis that the emission blueshift is primarily due to the screening of internal polarization fields, as this explanation neglects the contribution of plasma renormalization, which is nearly equal but opposite in magnitude. In contrast, the blueshift is explained only by accounting for a complex interplay of polarization-field screening, plasma renormalization, and phase-space filling. On the other hand, the spectral broadening occurs mainly due to phase-space filling. My analysis suggests that the key to improving the spectral characteristics of InGaN LEDs is to accelerate carrier recombination and transport and reduce the carrier density required to operate them at high power density. Finally, I investigate the concept of defect tolerance in InGaN emitters. Recent experiments have challenged the widely accepted hypothesis that carrier localization suppresses diffusion and enhances the tolerance of InGaN emitters to defects. By examining the competition between radiative and Shockley-Read-Hall recombination in InGaN alloys using a formalism that I recently developed, I propose that carrier localization and polarization fields enhance the quantum efficiency at low current densities, without invoking the suppression of carrier diffusion. Decreasing the oscillator strength or increasing the quantum-well thickness may improve the quantum efficiency of LEDs for low-power applications but it exacerbates efficiency droop and impair color purity control at high operating powers. Overall, this thesis paves the way for the continued development of III-nitride technology, and its approach can be generalized to other emerging semiconductors.

Power processing transforms energy to be used for work, extracted from clean power generation, or stored effectively and sustainably. This thesis investigates (1) power processing architectures and methods to harvest power in solar photovoltaic (PV) systems efficiently, (2) power processing architectures and methods to employ second-use battery energy storage systems (2-BESS) optimally, and (3) temperature measurement of wide-bandgap power semiconductors, which are widely used in solar PV systems and battery energy storage systems (BESS). The first part of this thesis focuses on architectures and methods for differential diffusion charge redistribution (dDCR) solar PV modules. These modules enable maximum power point tracking (MPPT) with cell-level granularity, which extracts nearly all the accessible power from each solar PV cell and is the best solution in terms of MPPT efficiency in solar PV systems. Since dDCR solar PV modules have two output ports, the conventional one-port hardware cannot be integrated with them. This thesis presents a new two-port up/down dc-dc MPPT converter and a new two-port hardware emulator for dDCR solar PV modules. Additionally, a new method for measuring diffusion capacitance in solar PV cells (an important parameter in dDCR modules) is introduced. The second and third parts of this thesis investigate power processing architectures and methods in 2-BESSs for dc and ac applications. BESSs play important roles in grids, such as supporting renewable power systems like solar PV systems, voltage and frequency regulation for grid power quality improvement, and supporting electric vehicle (EV) fast charging. At the same time, second-use batteries from the exponential growth of EVs represent a challenge. Reusing the second-use EV batteries for stationary applications introduces a sustainable approach and adds economic value to these batteries. This thesis presents a new stochastic method for lite-sparse hierarchical partial power processing (LS-HiPPP) architecture to optimize 2-BESS power processing over the lifetime degradation of batteries. Additionally, a framework for optimizing multilevel ac battery energy storage systems (MAC-BESS) is introduced, which is particularly advantageous for 2-BESSs. The fourth/last part of this thesis focuses on the accurate temperature measurement of the active area for wide-bandgap power semiconductors. High breakdown voltage, low on-resistance, and high speed have made wide-bandgap power semiconductors suitable for many applications, such as solar PV systems, BESSs, EVs, hybrid/electric aircraft, and wireless power transfer. However, the maximum power density of these devices is limited by the channel temperature rise. Thus, accurate temperature measurement of the active area is essential in research on wide-bandgap power semiconductors, often hampered by packaging and cooling methods.

The objective of this work is to leverage the unique insulator to metal transition of Lanthanum Cobaltite (LaCoO3, LCO) towards the next generation of power limiters for high temperature, wide bandwidth, and high-power operation. LaCoO3 is a semiconducting perovskite that demonstrates a spin-state transition to metallic behavior about 500 K. In this dissertation we establish a wafer-scale reactive sputtering deposition process, characterize the temperature-dependent properties of thin film LCO, and estimate the thermally driven band gap collapse by near-IR absorption measurements.The aforementioned sputtering process was used in the fabrication of power limiters that can be triggered either by external DC bias or by self-turn on at an input power threshold around 16 dBm. We present a 2 GHz LCO-based shunt power limiter constructed on silicon carbide with continuous wave power handling capability of 40 dBm, flat leakage of 20 dBm, and insertion loss less than 1 dB over a broad operating temperature range of 10 ᵒC to 75 ᵒC. Furthermore, very high temperature limiting response is recorded up to 225 ᵒC with a flat leakage of 15 dBm and power handling up to 33 dBm. LCO limiters of varied dimensions and geometries were studied to better understand the necessary tradeoffs in design for low insertion loss and high-power handling. To that end, a 3D COMSOL Multiphysics simulation was also developed that accurately predicts limiting performance and switching speed. This model is used to propose further improvements to the power limiter design. S-parameter testing was conducted from 0.1 to 50 GHz, verifying the broadband viability of LCO microwave devices. We present extremely low small signal losses, with a maximum insertion loss of 1.2 dB at 125 ᵒC and 50 GHz. Benchmarking against both recent research art and commercial products indicates that LCO is a strong candidate for the next generation of microwave power limiters. Finally, we conclude the thesis with an evaluation of an LCO-based series radio frequency switch fabricated on sapphire substrate. We further summarize and discuss the significant potential of LCO in a wide range of thermally or electronically driven switching applications.

Bidirectional power-transistor rectifier-inverter circuits have broad applications, ranging from uninterruptible power supplies, and electric vehicle motor drives, to renewable energy wind turbines. Sizable and expensive DC-link capacitors are commonly placed between the rectifier and inverter to decouple the circuit's nonlinear dynamics and facilitate control. Aiming to minimize the buffering capacitor and gain high performance for the nonlinear dynamics via the pulse width modulated (PWM) control of the transistor switches, this dissertation contributes to this field in three aspects. First, we developed a high-fidelity nonlinear discrete-time model of the continuous-time nonlinear system to facilitate model-based control design. This model is also more accurate than existing models published in the literature. Second, we proposed a novel framework of multi-input multi-output (MIMO) nonlinear model predictive control (NMPC), where both the non-linear model and approximate linearized model are used to strike the balance of the computational complexity and control performance. Third, we implemented the NMPC in real-time by field programmable gate array (FPGA), where the controller is modeled by a neural network trained offline by machine learning. We performed a simulation and experiment of the power converter control on a three-phase permanent magnet synchronous motor (PMSM) drive and demonstrated superior performance in comparison to the feedback linearization control (FBLC), power-balancing schemes, and conventional cascaded PI control.

Innovations within power electronics are necessary to enable future electric aircraft and space exploration. In these aerospace applications, power converters must be light-weight, efficient and reliable. Conventional, inductor-based, power electronics tend to be heavy, and have high switch stress making them difficult to implement in these applications. In this thesis, hybrid switched-capacitor converters are explored as they utilize energy-dense capacitors as the primary energy storage element, and also decrease the voltage stress of the switches. The basics of hybrid switched-capacitor converters are covered, with a focus on why these topologies are suitable for aerospace applications. Next, the losses of the capacitors, the main building block of these converters, are characterized and a model is proposed which allows for simple loss estimation. Then, the design and flight qualification of a hybrid switched-capacitor converter is discussed, showcasing a converter with high efficiency, power density and reliable control. Moreover, the safe control of hybrid switched-capacitor converters during shutdown is described, with a model proposed which allows designers to understand the shutdown of the converter and trade-offs in different shutdown techniques. Hybrid switched-capacitor converters are motivated for their use in harsh space environments, where radiation effects make designing high performance converters challenging. Two different converters designed for space applications are then described, utilizing techniques such as partial power processing to minimize passive component mass. Overall, this thesis showcases the design of several high performance hybrid switched-capacitor converters, but also introduces models and comparison frameworks to allow future designers to better understand the design and operation of hybrid switched-capacitor converters in aerospace applications.

Increase in greenhouse gas emission poses a threat to the quality of air thus threatening the future of living beings on earth. A large part of the emission is produced by transport vehicles. Electric vehicles (EVs) are a great solution to this threat. They will completely replace the high usage of hydrocarbons in the transport sector. Energy efficiency and reduced local pollution can also be expected with full implementation of electrification of transportation. However, the current grid is not prepared to take the power load of EV charging if it were to happen readily. Moreover, critics are doubtful about the long-term sustainability of EVs in terms of different supply chain issues. The first step for tackling this problem from a research perspective was to do a thorough review of the details of charging in modern day grid. The downsides and lack of futuristic vision. Findings showed that implementing end to end DC based on green energy aided by SiC power electronics. To prove the findings analysis and modelling was done for SiC based charging network. A similar approach was implemented in EV powertrain development. The implementation of SiC power electronics in charging network showed lesser losses, higher thermal conductivity, lesser charging time. The effect on long term battery health and additional circuit was also observed. The cost of production can be reduced by volume manufacturing that has been discussed. In powertrain analysis and simulation the loss and heat reduction one shown on a component-by-component basis. Therefore, this research proposes a Silicon Carbide based end to end DC infrastructure based completely on solar and wind power. The pollution will further be reduced, and energy demands will be met.

Since power converters shape a wide range of power electronic applications, the 'heart' of these conversions, such as solid-state switches, is crucial for achieving higher power density, lower loss, and higher efficiency operations. Although the limitations imposed by silicon-based power devices have been reduced by introducing novel devices such as IGBTs and super junction MOSFETs to allow for broader applications, solutions beyond silicon have presented a continuous challenge to the device engineers. Driving these converters at a higher switching frequency allows for higher power density. However, to support a higher frequency and operating temperature, superior materials, e.g., wide bandgap materials, are also needed. Two such materials, namely silicon carbide (SiC) and gallium nitride (GaN), thanks to their excellent material properties like higher mobility, higher breakdown electric field, and lower leakage, are paving the way to improved efficiency and high power density with broader functionality. Although SiC plays a vital role in a wider range of power electronics applications, the use of SiC outside of standard operation regions, e.g., cryogenic temperature (

Inverters are widely utilized in electric vehicle (EV) applications as a major voltage/current source for onboard battery chargers (OBC) and motor drive systems. The inverter performance is critical to the efficiency of EV system energy conversion and electronics system electro-magnetic interference (EMI) design. However, for AC systems, the bandwidth requirement is usually low compared with DC systems, and the control impact on the inverter differential-mode (DM) and common-mode (CM) performance are not well investigated. With the wide-band gap (WBG) device era, the switching capability of power electronics devices drastically improved. The DM/CM impact that was brought by the WBG device-based inverter becomes more serious and has not been completely understood. This thesis provides an in-depth analysis of on-board inverter control strategies and the corresponding DM/CM impact on the EV system. The OBC inverter control under vehicle-to-load (V2L) mode will be documented first. A virtual resistance damping method minimizes the nonlinear load harmonics, and a neutral balancing method regulates the unbalanced load impact through the fourth leg. In the motor drive system, a generalized CM voltage analytical model and a current ripple prediction model are built for understanding the system CM and DM stress with respect to different modulation methods, covering both 2-level and 3-level topologies. A novel CM EMI damping modulation scheme is proposed for 6-phase inverter applications. The performance comparison between the proposed methods and the conventional solution is carried out. Each topic is supported by the corresponding hardware platform and experimental validation.

The lighting industry was revolutionized with the emergence of LED lighting. Over the last 15 years, LED lighting device sales and utilization have grown immensely. The growth and popularity of LEDs is due to improved operation of the device when compared to previous lighting technologies. Efficient performance of the device is critical due to the growth of global energy consumption. As nonrenewable generation fuel is finite, utilities have begun the transition to renewable energy generation. Generation and distribution systems become inherently complex to comprehend and maintain with incorporation of emerging supply and load technologies. With the unprecedented growth of LED bulbs, there are concerns regarding the impact of their integration on power systems. In determination of the effects, which LED bulb adoption posed within the power grid, investigation of this device as a grid-load was pursued. This thesis reviews existing studies pertaining to LEDs and power grid load modeling methodologies. Load modeling aids in establishing a balance between energy generation and consumption, comprehensively characterizing relationships between electrical generation, transmission, distribution, and loads. Due to the complexities of large networked systems, device load models are constructed and aggregated in emulation of the interactive relationships throughout the power grid. This thesis includes a study of preestablished LED bulb ZIP load models and formulation of a component-based load model for improved characterization of a conventional LED lighting device. Load modeling was conducted with reference to the UTK HTB, for future integration and improved grid emulation. Factors, such as shape, size, illumination, and the power rating of popular LED bulbs is examined. Through investigation of typical LED bulb topologies, a model is formulated, in representation of device behavior as a load. The established load model’s characteristics are tested with comparison to physical device operation in a laboratory environment. The LED bulb component-based model is simulated under dynamic conditions in portrayal of device behavior under fault scenarios. An interactive interface is formulated for simulation of load behavior throughout grid level events. Detailed analysis of data and methods of implementation is provided, in characterization of the LED bulb’s load profile.

Silicon carbide (SiC) metal–oxide–semiconductor field effect transistors (MOSFETs) have seen rapid growth in recent years, thanks to its low conduction loss, fast switching speed, and good thermal conductivity. For high power applications, it is necessary to parallel two or more devices in order to achieve the desired current rating, conduction loss, and thermal performance. Traditional single-driver multi-chip module (SDM) requires strong drivers and suffers a lot from parasitic parameter mismatch induced transient current unbalance and intrinsic oscillation. To reduce the thermal imbalance and operation risks, the switching speeds of parallel MOSFETs or MOSFET modules in general are usually slowed with larger gate resistance, at the expense of higher switching loss. Therefore, this solution is not optimal since it indicates a poor utilization of the SiC MOSFET’s intrinsic high-speed capability. The research developed analytical models for the transient current sharing and inherent oscillation for two paralleled SiC MOSFETs’ switching process. The transient current sharing model is developed based on linearized circuit state equations, while the intrinsic oscillation model is based on small-signal equivalent circuits. By using these models, the influences of parasitic parameters are investigated. The optimized gate resistor selection to compensate circuit mismatches is discussed. Based on the studies and models, a 650 V, 300 A double-side cooling GaN HEMT based SDM is designed and fabricated. A better configuration of the multi-driver multi-chip module (MDM) is proposed and the performances are compared. The analytical models provide a fast way to evaluate and optimize the design or approach of any paralleled MOSFET cases. The proposed MDM solution could be a more efficient, more reliable power module design configuration. The parameter influence and comparison results were verified in the experimental tests.

The dissertation will present a systematic process for advanced characterization and control of a popular class of synchronous machines called Interior Permanent Magnet Synchronous Machines (IPMSM). The IPMSM machine exhibits several non-linear properties such as flux saturation and cross-coupling to name a few. Knowledge of the non-linear properties of the machine requires access to advanced design tools such as Finite Element Analysis (FEA) which may not be easily accessible within industries that do not design or manufacture these motors. The performance and efficiency of these motors are reliant on precise knowledge of advanced parameters. This body of work develops into two focus areas - experimental characterization of the IPM machine and Maximum Torque Per Amp (MTPA) based control of the machine using the experimental data. Firstly, the dissertation proposes an experimental method for extraction of Direct (D) and Quadrature (Q) axis flux linkages of the IPMSM considering both saturation and cross-magnetization effects over the entire range of the machine’s rated current. A key constraint placed is a standstill estimation of the machine in its targeted application. A novel method for generating the current pulse pattern is proposed which enables the automatic creation of 2D Flux Linkage maps of the motor using any standard controller. Analytical expressions are developed to determine the constraints for pulse pattern considering the power converter-based current control and minimizing rotor movement during the test. The flux maps obtained experimentally are seen to match the FEA-generated equivalent within an acceptable tolerance of error. The second focus area consists of developing MTPA control schemes that address practical issues such as complex offline/online calculations/excitation methods seen in classic literature. Initial research focused on developing an offline numerically efficient MTPA trajectory generation that uses FEA data to create a torque profile related to the optimal solution of net space vector current and corresponding current angle. Further research removed the dependency of the offline MTPA trajectory generation scheme on the FEA dataset by developing a method that utilizes simple motor datasheet parameters to get an initial non-efficient trajectory. This trajectory is fine-tuned during motor operation (online) via a novel discrete extremum-seeking state controller. While the offline method is shown to execute with minimal computational demand in a 32-bit MCU controller, the online method is shown to have comparable real-time performance while achieving equivalent MTPA tracking accuracy without introducing electrical or mechanical instability. Both methods have been implemented in a classic Field Oriented Control (FOC) scheme for the IPM motor using a standard 2-level Voltage Source Inverter (2L-VSI) prototype supplied from a 650V DC power supply. The methods have been experimentally verified on a 3 HP dynamometer with custom-built data acquisition instrumentation as well as software. Experimental results show good correspondence to simulations thus proving the effectiveness of the proposed methods.

Surge-energy robustness is essential for power devices in many applications such as automotive powertrains and electricity grids. While Si and SiC MOSFETs can dissipate surge energy via avalanche, the GaN high-electron-mobility transistor (HEMT) has no avalanche capability and withstands surge energy by its overvoltage capability. However, a comprehensive study into the surge-energy robustness of the cascode GaN HEMT, a composite device made of a GaN HEMT and a Si metal-oxide-semiconductor field-effect-transistor (MOSFET), is still lacking. This work fills this gap by investigating the failure and degradation of 650-V-rated cascode GaN HEMTs in single-event and repetitive unclamped inductive switching (UIS) tests. The cascode was found to withstand surge energy by the overvoltage capability of the GaN HEMT, accompanied by an avalanche in the Si MOSFET. In single-event UIS tests, the cascode failed in the GaN HEMT at a peak overvoltage of 1.4~1.7 kV, which is statistically lower than the device's static breakdown voltage (1.8~2.2 kV). In repetitive UIS tests, the device failure boundary was found to be frequency-dependent. At 100 kHz, the failure boundary (~1.3 kV) was even lower than the single-event UIS boundary. After 1 million cycles of 1.25-kV UIS stresses, devices showed significant but recoverable parametric shifts. Physics-based device simulation and modeling were then performed to understand the circuit test results. The electron trapping in the buffer layer of the GaN HEMT can explain all the above failure and degradation behaviors in the GaN HEMT and the resulted change in its dynamic breakdown voltage. Moreover, the GaN buffer trapping is believed to be assisted by the Si MOSFET avalanche. An analytical model was also developed to extract the charges and losses produced in the Si avalanche in a UIS cycle. These results provide new insights into the surge-energy and overvoltage robustness of cascode GaN HEMTs.

Power electronic advancement trends indicate that device power density will continue to increase as a result of increased power requirements and desired device form factor reduction in order to reduce weight and material costs and increase ease of integration into next-generation power systems. With these advancements come concerns regarding device reliability. The compounded effects of increased power density and form factor reduction in electrical conductors will yield amplified joule heating effects in addition to the already increasing device temperature profiles resulting from the incorporation of wide bandgap technology into power systems. Joule heating effects can lead to a variety of reliability problems, but there are two failure modes which pose serious potential threats for devices in the future. In electrical conductors, one phenomenon associated with elevated temperatures and power densities is electromigration. Electromigration refers to the migration of conductor material away from its initial position and is typically associated with electrical resistance increases and shorting. The second potential failure mode is related to thermomechanical stresses resulting from differing coefficients of thermal expansion at localized hot spots in a device. One of the most common ways to make connections inside of power electronic devices is by wire bonding. Small current carrying components, such as wire bonds, in power electronic devices may be subjected to a combination of electromigratory and thermomechanical related stresses during operation. Thus, it is advantageous for studies to be conducted to understand the impact that the combined effects of electromigration and mechanical stress have on wire bond reliability. This work introduces a novel accelerated test methodology for divulging the impacts of these combined effects on wire bonded interconnects and introduces a framework for reliability analysis based on accelerated testing methodologies.

Current sharing schemes for conventional multi-phase converters are based on sensing each phase current to deliver the current information to their controllers. In conventional buck converters, this fact may require a preset current sharing ratio at the expense of efficiency, which eventually requires a larger sensing circuit to achieve the sensing accuracy of each phase. Introducing the concept of automatic current sharing is one of the solutions to tackle this issue. Automatic current sharing (Current Sharing Mechanism CSM) is an advanced way to distribute heat generation in multi-phase switching topologies at full load. A two-phase series capacitor buck converter (2-pscB) was introduced to power laptops as low-voltage and high-current Voltage Regulator Modules (VRMs) as well as non-isolated Point-of-Load (PoL) converters. The current sharing concept is the main feature of this 2-pscB topology, where series capacitor voltage is used to achieve current sharing without the need for a phase current sensing circuit or complicated control loop. In this work, a complete state-space average model for the series capacitance buck switching regulators is linearized to develop a robust controller satisfying the stability and converter performance specifications. The presented averaging model includes the simplest model of the regulator’s parameters and only the main parasitic components. Both, an improved derivation of the main design parameters and a novel design methodology of MOSFETs isolated gate driver circuit are proposed and verified. Different high voltage input 2-pscB power density dc-dc converters are successfully investigated to examine the capability of current sharing at a higher voltage level and its impact on efficiency. Another novel approach of eGaN gate driver circuitry is designed with a Current-Mode Controller CMC using one current path to minimize propagation delays and reduce phases parasitic components, which helps enhance overall performance. 110V/12V/6A experimental prototype converter of Si MOSFETs was designed, its current sharing characteristics were experimentally tested and verified. Since eGaN technologies have attracted great attention in power electronics applications due to their capabilities and efficient energy conversion, another design, and analysis of a sensor-less eGaN-based 48V/5V 2-pscB buck switching converters were verified, and their current sharing characteristics were predicted by the state-space modeling technique. A theoretical comparison is conducted between conventional buck converter and 2-pscB. The results show the following characteristics of 2-pscB topology: a small inductor current ripple, low switching loss, inherited current sharing mechanism, duty cycle flexibility, and filter component size reduction. In a word, new modeling methods of various 2-pscB control schemes are proposed and broadly studied. This dissertation simulates most of these methods to provide the designers with a better comprehensive view of the 2-pscB converter topology.

The third quadrant (3rd-quad) conduction (or reverse conduction) of power transistors is critical for synchronous power converters. For power metal-oxide-semiconductor field-effect-transistors (MOSFETs), there are two current paths in the 3rd-quad conduction, namely the MOS channel path and the body diode path. It is well known that, for 1.2 kV silicon carbide (SiC) planar MOSFETs, the conduction loss in the 3rd-quad is reduced by turning on the MOS channel with a positive gate bias (VGS) and keeping the dead time as small as possible. Under this scenario, the current is conducted through both paths, allowing the device to take advantage of the zero 3rd-quad forward voltage drop (VF3rd) of the MOS channel path and the small differential resistance of the body diode path. However, in this thesis work, this popular belief is found to be invalid for power MOSFETs with higher voltage ratings (e.g., 3.3 kV and 10 kV), particularly at high temperatures and current levels. The aforementioned MOS channel and body diode paths compete in the device’s 3rd-quad conduction, and their competition is affected by VGS and device structure. This thesis work presents a comparative study on the 3rd-quad behavior of 1.2 kV to 10 kV SiC planar MOSFET through a combination of device characterization, TCAD simulation and analytical modeling. It is revealed that, once the MOS channel turns on, it changes the potential distribution within the device, which further makes the body diode turn on at a source-to-drain voltage (VSD) much higher than the built-in potential of the pn junction. In 10 kV SiC MOSFETs, with the MOS channel on, the body diode does not turn on over the entire practical VSD range. As a result, the positive VGS leads to a completely unipolar conduction via the MOS channel, which could induce a higher VF3rd than the bipolar body diode at high temperatures. Circuit test is performed, which validates that a negative VGS control provides the smallest 3rd-quad voltage drop and conduction loss at high temperatures in 10 kV SiC planar MOSFET. The study is also extended to the trench MOSFET, another major structure of commercial SiC MOSFETs. Based on the revealed physics for planar MOSFETs, the optimal VGS control for the 3rd-quad conduction in different types of commercial trench MOSFETs is discussed, which provides insights for the design of high-voltage trench MOSFETs. These results provide key guidelines for the circuit applications of medium-voltage SiC power MOSFETs.

Global energy consumption continues to grow, driving the need for cheap, power-dense power electronics. Replacing the incumbent silicon insulated gate bipolar transistors with silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) has been proposed as a solution to increase the power densities of power converters in some applications. One such application is electric vehicles (EVs) where the efficiency and weight of the power electronics are critical; however, modern packaging technologies are still limiting the performance of SiC MOSFETs. One promising trend in power semiconductor packaging technologies is the use of printed circuit boards (PCBs) because the technology is mature—resulting in low costs—and the allowable stackups are ideal for integrating driving circuitry and power loop components—resulting in reduced manufacturing complexity. This thesis presents the design and analysis of two PCB-embedded 1.2 kV SiC MOSFET half-bridge packages and a hybrid PCB/DBC-based 1.2 kV SiC MOSFET full-bridge package for EV on-board charger applications. The first of the two PCB-embedded packages has integrated gate drive circuitry, less than 2.3 nH loop inductances, and dual-sided cooling with a total junction-to-case thermal resistance (RTH,JC) of 0.12 K/W. The second PCB-embedded package has only drain-side cooling to allow for surface mount terminals, has an area of 37.1 mm x 18.5 mm due to the removal of the gate drive circuitry, and has less than 2.4 nH loop inductances. The PCB/DBC-based full-bridge package has an RTH,JC of 0.65 K/W, less than 4.5 nH, and integrated gate drive circuitry.

Semiconductors have unique electrical properties such as variable electrical conductivity through doping, making them an essential component of modern electronics. Silicon is the traditional semiconductor material that governs modern microelectronic technology. However, with the advent of artificial intelligence (AI), big data, autonomous vehicles, and Internet of Things (IoT), there is a need for developing advanced semiconductor materials that can operate more energy-efficiently at high power and high frequency. Power electronics is the application of electronics to the control and conversion of electrical power and it seeks to enhance energy conversion efficiency by utilizing ultra-wide-band-gap (> 3.4 eV, UWBG) semiconductors with high carrier mobility and high thermal conductivity. However, materials with wide band gaps generally have heavy effective masses which lead to inefficient charge transport and doping. The state-of-the-art materials suffer from doping asymmetry and/or poor thermal conductivity, which motivates alternative UWBG semiconductors with enhanced material properties. This thesis investigates theoretical discovery and experimental synthesis of novel UWBG semiconductors that can overcome the challenges faced by the state-of-the-art materials. To discover the extreme limits to semiconductor band gap, wide-band-gap materials are surveyed and the key material factors are identified which enables semiconductivity of materials. It is found that materials composed of light elements and crystallized in densely packed structures give rise to a combination of wide band gap and light effective mass that enables shallow dopant, high mobility, and weakly bound polarons. For the candidate semiconductors, atomistic calculations are performed to explicitly calculate dopant ionization energies, formation of DX centers, and carrier mobility. Calculation results revealed promising semiconductor materials with band gaps up to 11.6 eV (even wider than insulators), which challenges the conventional gap-based criterion to distinguish semiconductors from insulators. Among the materials, rutile GeO2 (r-GeO2) is identified to be a promising, yet unexplored UWBG (4.68 eV) semiconductor for rapid transformative impact of power electronic applications. Hybrid density functional theory predicted shallow ionization energies for donors such as SbGe, AsGe, and FO, and the ionization energy of 0.45 eV for Al acceptor that can be lowered by heavy Al doping to enable ambipolar doping. The electron and hole mobilities are also calculated (289 cm2 V−1 s−1 and 28 cm2 V−1 s−1, respectively), which are close to the state-of-the-art semiconductors such as GaN. Thermal conductivity is also measured for hot-pressed r-GeO2 polycrystals using laser-flash. The measured value is 51 W m−1 K−1, 3 times higher than β-Ga2O3. Though thin film growth of r-GeO2 is challenging due to the presence of kinetically stable glass phase and high vapor pressure of GeO, the first synthesis of single crystal r-GeO2 thin films is demonstrated using molecular beam epitaxy. Due to the competitive phase space, growth conditions that utilize a novel preoxidized molecular precursor as well as buffer layers with reduced misfit strain are key to realizing the rutile phase. Though the available substrates all have large lattice difference with r-GeO2 (> 4%), flux synthesis technique and mechanical polishing allow the fabrication of 4 × 2 mm2 size r-GeO2 single crystal substrates with highly crystalline surfaces that can be utilized for epitaxial film growth. This work provides opportunities to realize new UWBG semiconductors with enhanced material properties that can drive energy-efficient power electronics.

VSC-HVDC (voltage source converter based HVDC) system with its inherent merits for renewable energy integration has captured increasing research attentions. However, compared with AC systems dominated by synchronous generators (SGs), VSC-HVDC systems with general vector control cannot provide inertia for the grid due to lack of kinetic energy. This tends to degrade the safety and stability of the grid with the increasing penetration of renewable energy sources. To cope with this issue, virtual synchronous generator (VSG) has been proposed. In this thesis, firstly, a comprehensive introduction of various typologies of VSG schemes is made to illustrate their deficiencies and merits. The simulation results established in Simulink/Plecs show that VSG can not only participate into the regulation of frequency and voltage in case of power disturbances but guarantee the inertia provision for the grid. Although the integration of VSG control enhances the inertia and damping response of inverts, researches show that plenty of issues relative with VSG should be ameliorated. The fluctuation performances of SGs are introduced into the output active power and current of inverters when incorporates VSG control. This threatens the stability and safety of VSG operation, for power electronic based inverters are more vulnerable during the oscillations of current and frequency. Hence, to solve these issues, various enhanced VSG strategies have been constructed to improve its robustness and output performance. In this thesis, the structures and properties of enhanced VSG schemes are fully discussed. The results show that the dynamic properties of VSG during transient periods are enhanced in comparison of that of normal VSG. Modular multilevel converters (MMC) and alternate arm converters (AAC), as the representatives for enhanced topologies of VSC-HVDC system, have more complicated inner structures in comparison with 2/3 level converters. In this thesis, VSG control is applied into MMC/AAC models to strengthen their power and frequency regulation ability. In addition, a four-terminal multi terminal direct current (MTDC) system is incorporated with VSG control to provide primary frequency and voltage response for the grid. The results show that the integration of VSG improves the stability operation and inertia response of MMC/AAC/MTDC systems.

The continual increase in performance and feature densities of small form factor mobile products has driven the need for high-capacity batteries and thus battery charger solutions with higher power-delivery densities to meet the demand for reduced charging times. The USB- C power delivery specification was developed to meet these higher demands by providing a programmable VBUS voltage range of 5–20 V with up to 100 W of power delivery, which serves as the input voltage (VIN) for the battery charger. A DC-DC converter that efficiently takes advantage of this wide VIN range while providing an output voltage (VO) range suitable for battery charging (e.g. 2.8V–4.2V) is challenging but highly desirable for space constrained products.Hybrid converters provide a path to meet these challenges by leveraging the benefits of both switched-capacitor (SC) and switched-inductor (SI) techniques to reduce inductor size and efficiently provide high VIN⁄VO voltage conversion ratios (VCRs). The former is important since inductors have substantially lower energy storage densities compared to modern capacitor technologies. Therefore, inductors tend to be the largest occupiers of board space and bill-of- material cost out of all the converter passives. Additionally, die-level or package-level integration of high quality inductors can be challenging when compared to capacitors.This work intends to address these challenges by introducing new hybrid converter topologies that reduce the energy processing required by the inductor while still achieving the VCRs needed to take advantage of the benefits offered by higher VIN charging. This reduces the reliance on large, high quality inductors to maintain high power efficiency. The first part of this dissertation provides background regarding charge-based converter analysis. The next part presents a flying inductor hybrid topology that relocates the inductor from the high output current location to lower input current location while providing multiple outputs for 1-cell and 2-cell charging. The last part presents a single inductor multi-stage hybrid converter that utilizes an inductor to couple two SC stages to provide soft-charging benefits to each stage while leveraging reconfiguration to efficiently provide a wide range of VCRs.

Gallium Oxide (Ga2O3) is an ultra-wide bandgap semiconductor with a bandgap of 4.5–4.9 eV, which is higher than the bandgap of Silicon (Si), Silicon Carbide (SiC), and Gallium Nitride (GaN). A benefit of this wide-bandgap is the high critical electric field of Ga2O3, which is estimated to be from 5 MV/cm to 9 MV/cm. This allows a higher Baliga’s figure of merit (BFOM), i.e., unipolar Ga2O3 devices potentially possess a smaller specific on-resistance (Ron,sp) as compared to the Si, SiC, and GaN devices with the same breakdown voltage (BV). This prospect makes Ga2O3 devices promising candidates for next-generation power electronics. This thesis explores the design, fabrication, and packaging of vertical Ga2O3 Schottky barrier diodes (SBDs). The power SBD allows for a small forward voltage and a fast switching speed; thus, it is ubiquitously utilized in power electronics systems. It is also a building block for many advanced power transistors. Hence, the study of Ga2O3 SBDs is expected to pave the way for developing a series of Ga2O3 power devices. In this work, a vertical β-Ga2O3 SBD with a novel edge termination, which is the small-angle beveled field plate (SABFP), is fabricated on thinned Ga2O3 substrates. This SABFP structure decreases the peak electric field (Epeak) at the triple point when the Ga2O3 SBD is reverse biased, resulting in a BV of 1.1 kV and an Epeak of 3.5 MV/cm. This device demonstrates a BFOM of 0.6 GW/cm2, which is among the highest in β-Ga2O3 power devices and is comparable to the state-of-the-art vertical GaN SBDs. The high-temperature characteristics of Ga2O3 SBDs with a 45o beveled angle sidewall edge termination are studied at temperatures up to 600 K. As compared to the state-of-the-art SiC and GaN SBDs with a similar blocking voltage, the vertical Ga2O3 SBDs are capable of operating at higher temperatures and show a smaller leakage current increase with temperature. The leakage current mechanisms were also revealed at various temperatures and reverse biases. A new fabrication method of a dielectric field plate and Ga2O3 mesa of a medium angle (10o~30o) is achieved by controlling the adhesion between the photoresist (PR) and the dielectric surface. As compared to the small-angle termination, this medium-angle edge termination can allow a superior yield and uniformity in device fabrication, at the same time maintaining the major functionalities of beveled edge termination. Good surface morphology of the field plates and Ga2O3 mesa of the medium angle 10o~30o sidewall angle is verified by atomic force microscopy. Finally, large-area Ga2O3 SBDs are fabricated and packaged using silver sintering as the die attach. The sintered silver joint has higher thermal conductivity and better reliability as compared to the solder joint. The metal finish on the anode and cathode has been optimized for silver sintering. Large-area, packaged Ga2O3 SBDs with an anode size of 3×3 mm2 are prototyped. They show a forward current of over 5 A, a current on/off ratio of ~109, and a BV of 190 V. To the best of the author’s knowledge, this is the first experimental demonstration of a large-area, packaged Ga2O3 power device.

The reliability of electronic devices is dependent upon the conditions to which they are subject. Temperature variations coupled with differences in thermal expansion between bonded materials results in thermomechanical stresses to build up, which can instigate failure in the interconnects or other critical regions. With the move towards electrification in the automotive industry, there is the increasingly important consideration of powertrain electronics reliability, the pertinent conditions being governed by the drive cycle or mission profile of the vehicle. The mission profile determines the power dissipated by the electronic devices, which determines the peak and mean temperature, temperature swing and the resultant stress range, as well the effective thermal cycling frequency. This thesis, submitted in partial completion of the requirements for the Master of Science in Mechanical Engineering, herein investigates the relationship between predicted lifetime of electronic components in the drivetrain of an electric or hybrid electric vehicle and the mission profile it is operated at. The primary datasets are taken from the Environment Protection Agency (EPA) fuel economy test cycles, which lists various standard mission profiles for different driving conditions. The thermal profiles resulting from each mission profile are used to extract damage parameters and used to estimate time to failure. As the lifetimes are dependent on the thermal transients, ways are explored to minimize the temperature swings. One such way is to use phase change materials as thermal reservoirs that can be very effective thermal management option under the right conditions. Phase change materials absorb thermal energy as latent heat, which allows them to absorb a very large amount of heat per unit volume, but they are limited by low thermal conduction and long regeneration times. An affordable and widely available phase change material, paraffin, is used as a case study. A model is developed to mimic a widely available commercial power module, and detailed parametric studies are done to understand the effectiveness and best practices in using paraffin as a phase change material in cooling. The results show that PCMs hold great potential in automotive electronics cooling, but there is a delicate trade-off between the latent heat, thermal conductivity, and dissipated power that can be handled. As coefficient of heat transfer of secondary cooling mechanism gets larger, using PCMs become less advantageous.

The increase in energy demanded by transportation and energy sectors has necessitated highly efficient thermal management for reliable power electronics operations. Conventional cooling techniques are limited by their inability to target switching location hot spot temperatures, leading to non-uniform thermal gradients. These devices, such as cold plates and heat sinks, also utilize heavy metallic structures that can accentuate electromagnetic interferences generated by high voltage switching processes. This work proposes a non-metallic jet impingement cooler for more customized thermal management, while simultaneously reducing the harmful effects of electromagnetic interferences. Additive manufacturing is utilized to enable jet impingement zones to target individual power module hot spots in a lightweight, electrically isolating framework. Simulated and experimental results with die-mimicking capabilities show the ability of reducing maximum junction temperatures by 30 °C and eliminating cross-module temperature gradients by 90%. Integrated testing with a 150kW silicon carbide MOSFET based inverter show a 25dB drop in common mode noise as a result of a 99% reduction in parasitic capacitance pathways through the thermal management system. Furthermore, multiple jet impingement devices integrated with a single-phase inverter setup is demonstrated as a method to thermally balance electrical devices through hydraulic circuit networks.

Abstract: Dual inverter topologies can produce multilevel output voltage waveforms and have multiple degrees of freedom in control. Due to their versatility and modular nature, they find many different applications in power electronics. Although these topologies have been in existence for almost three decades, there is still room for improvement in terms of their utilization. The aim of this work is to further utilize the capabilities of these topologies in existing dual inverter applications and to explore new opportunities in applications that could benefit from their use. Two dual inverter structures are explored in this thesis. The first is an existing topology: the dual inverter drive using a floating capacitor bridge. This topology can provide induction machines with a reactive voltage boost extending their speed range without increasing supply voltage requirements. However, this presents some unique challenges with respect to drive modulation and capacitor voltage control. These challenges are addressed through the development of a new carrier based PWM scheme and a control strategy. The PWM scheme is able to produce high quality 5-level PWM line voltage waveforms regardless of the difference in phase or modulation depth between inverters. This improves the motor current THD and harmonic volt-seconds, reducing high frequency motor losses. The proposed control strategy uses a stator current reference frame that is able to decouple the motor and capacitor dynamics such that the capacitor voltage can be maintained constant during motor transients. This allows the floating bridge capacitor size to be reduced by a factor of more than ten compared to existing works. Additionally, the use of this reference frame provides an extra voltage boost that reduces supply voltage requirements by 26%. The second dual inverter structure studied utilizes a center-tapped open-ended winding grid transformer to produce new topologies with enhanced capabilities. Two new multiport topologies are derived for application in the emerging landscape of hybrid AC/DC grids where high penetration of renewable DC energy sources and storage is needed. Dual inverter topologies are ideal for such applications due to their multiple AC/DC ports and degrees of freedom in control. The first topology derived is for bipolar DC distribution that is capable of performing the two tasks of exchanging power between the AC grid and bipolar DC grid, while keeping the DC pole voltages balanced without the use of additional components or penalties on component ratings. The second topology is a multiport DC/DC/AC converter which is suitable for applications such as renewable energy integration with battery energy storage, or DC fast charging. The topology significantly increases the power transfer limits of the ports compared to using multiple separate converters. Both topologies allow bidirectional single stage power transfer between their ports, reducing the number of conversion stages and losses. This is made possible by a control strategy developed to decouple AC and DC power transfer mechanisms. Through the use of these mechanisms and the multi-tasking of inverters, the capabilities of the two dual inverter topologies are significantly enhanced compared to two inverters operated independently.

Abstract: Galvanic isolation using transformers is an important feature of many power converters, providing additional safety by separating the ground potential of two or more sections of an electrical system. High-frequency (HF) transformers increase the power density of converters by reducing the core size and weight. A further increase in power density can be achieved by using a single power conversion stage. Two single-stage power converter systems offering HF isolation are presented: a dc to ac converter and a multiport topology. The converters take advantage of the differential (DM) and common-mode (CM) currents that can be driven using center-tapped transformers connected to dual inverters. The DM currents are generated as HF three-phase sinusoidal currents to achieve power control through the transformers, introducing a straightforward alternative approach to the conventional dual active bridge (DAB) concept, where square-wave voltages are phase shifted to control HF transformer power transfer. The CM currents are generated as low-frequency (LF) currents for ac grid power exchange. A multi-frequency pulse-width modulation (PWM) scheme is employed to generate these current components. Independent control of HF transformer power and LF ac power can be realized using well-established control techniques, such as dq-frame current control, simplifying the implementation of the converter concept. Both converter systems are experimentally validated, showing that decoupled control of ac grid power and HF transformer power can be attained. Moreover, the converters are shown to have reduced ac output filtering requirements than two-level voltage-source converters. The multiport converter concept is among a very limited number of single-stage converters offering HF isolation that can realize ac-ac power conversion.

Semiconductor switching device parameters change with aging. This degradation reduces power electronics' performance and eventually results in failure of the circuitry. To prevent this from occurring, many researchers have identified precursors to failure. This research presents the damage indicators unique to repetitive, short circuit conditions in different SiC power devices and Si IGBTs. It investigates how the conducted electromagnetic interference (EMI) signature changes with aging, the degrading parameters behind the change and proposes a methodology to determine the fault location. This research also examines using EMI measurements to assess the health of commercially available SiC MOSFETs, SiC cascodes, and Si IGBTs. The devices were aged via repetitive short-circuit events without exceeding the components' critical energy. They are characterized by measuring the change in switching characteristics, EMI signature and device-specific parameters. SiC and Si devices age in different ways under repetitive short-circuit events. The variety of parameter degradations indicates that the devices' fault location is not the same, contributing to different changes in the EMI spectrum. Notable changes were seen in the IGBT's EMI spectrum and SiC devices at a specific frequency range due to device degradation.

Due to narrower bandgap and lower critical electric field, silicon (Si) power devices have reached their limit in terms of the maximum blocking voltage capability. Exploiting this limitation, wide bandgap devices, namely silicon carbide (SiC) and gallium nitride (GaN) devices, are increasingly encroaching on the lucrative power electronics market. Unlike GaN, SiC devices can exploit most of the established fabrication techniques of Si power devices. Having substrate of the same material, vertical device structures with higher breakdown capabilities are feasible in SiC, unlike their GaN counterpart. Also, the excellent thermal conductivity of SiC, compared to GaN and Si, let SiC devices operate at higher temperatures (~ 300°C). Hence, a more compact and cost-effective power electronic system can be designed with SiC devices without cumbersome cooling requirements. Specifically, SiC power MOSFETs have started to dominate applications such as three-phase inverters, PWM rectifiers, DC-DC converters in the 1.2 kV – 3.3 kV voltage range. However, SiC power MOSFET's full potential can only be harnessed with accurate and efficient simulation tools that enable optimally designed systems without multiple cost and time-consuming prototyping. Significant work has already been done on the compact modeling of SiC power MOSFET. However, those works focus on the first quadrant behavior. The third quadrant behavior, especially the gate bias dependent body diode characteristics, needs proper modeling for synchronous rectification, freewheeling diode action, dead time optimization, and EMI analysis. Further, the existing physics-based compact models lack efficient and continuous temperature scaling, which is essential for efficient and accurate simulation of power electronic systems with significant self-heating. This dissertation reports on an accurate and efficient electro-thermal model of the SiC power MOSFET that will include the third quadrant behavior with the body diode. In modeling body diode characteristics, the gate bias dependency and reverse recovery are included for the first time. For accurate switching characteristics, gate dependency of the input capacitance has been included. Accurate Miller capacitance modeling both at very low bias and at very high bias is ensured without adding too many model parameters. Avalanche-induced breakdown characteristics are included to make the model capable of predicting Safe Operating Area (SOA). Double pulse tests (DPT) at various temperatures were performed to validate the model's switching characteristics accuracy. A buck converter was implemented with the same half-bridge configuration as the DPTs to validate the model's performance with self-heating effects. Various other power electronics topologies are simulated to validate the accuracy and efficiency of the developed model. Detailed comparison with a previous physics-based model and a vendor-provided empirical model highlights the importance of the developed model in terms of accuracy and efficiency. Lastly, an easy-to-follow parameter extraction procedure has been described to enable broader use of the model among power electronics designers.

As power electronic system (PES) continue to incorporate complex intra-system communication, understanding and characterizing this communication has become a complex task. Knowing how a system’s communication will behave is vital to ensuring proper operation of these systems. This thesis proposes and outlines a communication testbed that streamlines the development and testing of the communications between the components of PES, and further presents the characterization of communication protocol utilized in these multi-agent PESs. These communication protocols include MQTT, Modbus, or User Datagram Protocol (UDP). Understanding the different behavior of these protocols presents is paramount for the design of PESs.

A finite element analysis (FEA) driven, automated numerical optimization technique is used to design electric field grading structures in a PCB-integrated bus bar for a 10 kV bondwire-less silicon-carbide (SiC) MOSFET power module. Due to the ultra-high-density of the power module, careful design of field-grading structures inside the bus bar is required to mitigate the high electric field strength in the air. Using Bayesian optimization and a new weighted point-of-interest (POI) cost function, the highly non-uniform electric field is efficiently optimized without the use of field integration, or finite-difference derivatives. The proposed optimization technique is used to efficiently characterize the performance of the embedded field grading structure, providing insights into the fundamental limitations of the system. The characterization results are used to streamline the design and optimization of the bus bar and high-density module interface. The high-density interface experimentally demonstrated a partial discharge inception voltage (PDIV) of 11.6 kV rms. When compared to a state-of-the-art descent-based optimization technique, the proposed algorithm converges 3x faster and with 7x smaller error, making both the field grading structure and the design technique widely applicable to other high-density high-voltage design problems.