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Abstract: Grid-tied power converter system is the key link in many power conversion applications such as renewable energy power generation, changing of electric vehicle, and industry motor drives. The performance of the grid interfacing converter has a substantial impact on the overall performance of the entire system. One popular design concept of the grid-tied converter system is adopting modular parallel converters. With such design, system reliability can be enhanced and efficiency improvement is achievable. To further elevate system performances, interleaving technique is a promising approach to operate the parallel converters. In spite of the advantages of parallel modularity and interleaving technique, recent development trend has imposed further challenging requirements on converter system design.High power density is one of the key challenges. Specifically for modular parallel converters, the common mode circulating current (CMCC), as a side effect of interleaving technique, will increase the size of the common mode (CM) choke in each converter module. To fulfill the power density requirement, minimizing CMCC is a mandate.In parallel to the power density requirement, stable operation of grid-tied converters is another critical issue. With the increasing penetration of LCL-filtered power converters in the utility grid, the filter resonance issue has become a sever challenge. Eliminating the LCL filter, and thus the filter resonance related issues, while maintaining small filter size and grid code compatible current quality is highly desirable, but also a challenging task.The focus of this thesis is thus situated on the addressing above challenges and seeking potential opportunities for further improvements. To reduce CMCC while preserving parallel modularity, the first step is a comprehensive harmonic distribution analysis for generalized pulse width modulation (PWM) schemes. The analysis results in a two-degree-of-freedom (2DoF) interleaving scheme which can effectively minimize the CMCC in modular parallel converter system regardless the number or type of the converters. In addition, leveraging the interleaving technique, a new system design concept is proposed to eliminate the LCL filter in each converter module. A comprehensive system level design analysis indicates that only small L filter is required to meet the grid code when there are five or six interleaved converter modules in a system. As such, the filter resonance related issues can be completely eliminated. More importantly, the total filter size with the proposed design can be substantially reduced as compared to the LCL filter based design. To further enhance system performances, a novel multilevel converter topology concept, i.e. internal parallel converter (IPC), is proposed to integrate parallel modularity and interleaving technique into one multilevel converter. A high density Gallium Nitride (GaN) device based IPC prototype is also developed in this thesis as a demonstration.

As the trend towards vehicle electrification, renewable energy, smart systems is increasing, the key enabling technology such as power electronics are becoming ever more important. Power electronics is the vital component of many applications in automotive, computer, data-centers, medical, aerospace, communication, green-energy, and manufacturing sectors. Major advancements in high efficiency, high power density, high voltage conversion ratio, and fast dynamic response power-electronic converters is evident both in research and industry, particularly at the topology level. A major contribution of this dissertation is the analysis, design, development, and dynamic modeling of a novel impedance-source topology termed as A-source converter, which potentially satisfies all the above factors.The pulse-width modulated (PWM) A-source converter exhibits the following attractive features: (a) high voltage step-up with low parts count, (b) continuous input current, (c) magnetically coupled impedance-source nature, (d) scalable design, and (e) configurable as dc-ac inverter or dc-dc converter. In this dissertation, the steady-state analysis of the converter waveforms, the derivation of the component design equations, and component voltage and current stresses are derived for the converter operated at continuous-conduction mode (CCM). A design procedure is also provided for a converter operated at a supply voltage of 12 V, output voltage of 48 V, and switching frequency 50 kHz. Another major contribution of the dissertation is the development of the dynamic model of the converter power-stage and that for closed voltage-mode operation. By the principle of circuit-averaging, the expressions for the averaged transistor current and diode voltage are obtained and an equivalent dc model is developed. By perturbing the steady-state model about its dc operating point and performing linearization, the small-signal model is developed. Subsequently, the small-signal transfer functions and network impedances are derived. The dynamic frequency- and time-domain properties of the power-stage are analyzed in details. Voltage-mode control of the A-source converter is designed and characterized. The closed voltage-loop transfer functions are derived. A laboratory prototype of the A-source dc-dc converter was designed, built, and tested for the above-mentioned specifications. The open-loop power-stage and closed voltage-loop transfer functions were measured using the gain-phase analyzer. An excellent agreement between the theoretical and measured results were observed, thereby, validating the predicted results. The A-source topology belongs to the class of boost-type high voltage step-up converters. Such boost-type converters have non-minimum phase properties and the dynamic models contain a right half-plane (RHP) zero. Future work in this area constitutes a study of the stability and sensitivity of the RHP zero to change in supply voltage and load resistance.

In this research, a time-based oversampling delta-sigma (ΔΣ) ADC architecture is introduced. This system uses time, rather than voltage or current, as the analog variable for its quantizer, and the noise shaping process is realized by modulating the width of a variable-width digital “pulse.” The ΔΣ loop integrator, the quantizer and digital-to-analog converter (DAC) are all time-based circuits and are implemented using digital gates only. Hence, no amplifier or voltage-based circuit is required. The proposed architecture not only offers a viable for nano-scale ‘digital’ IC technologies, but also enables improved circuit performance compared to the state-of-the-art. This is in contrast to conventional voltage-based analog circuit design, whose performance decreases with scaling due to increasingly higher voltage uncertainty due to supply voltage. The proposed architecture allows all digital implementation after the Voltage to Time Converter (VTC) and merged multi-bit quantizer/DAC blocks by taking advantage of delay lines reusable in both quantization and DAC operation. The novelty of this architecture is digital pulse width processing to implement the ΔΣ modulation. It is realized with small area and potentially can take advantage from the process scaling. A 3-bit prototype of this ADC in 0.18 μm CMOS process is implemented, tested, and presented. With an OSR of 36 and a bandwidth of 2 MHz, it achieves a SNDR of 34.6 dB while consuming 1.5 mA from a 1.8 V supply. The core occupies an area of 0.0275 mm² (110μm × 250μm = 0.0275 mm²). The second generation of the architecture was fabricated in IBM 45 nm SOI process. The oversampling frequency of this system is 705 MHz and oversampling ratio of 64. The expected performance is 7-bit effective resolution for a 5.5 MHz bandwidth while consuming 8mW of power and occupying a core area of less than 0.02 mm² (160μm × 120μm = 0.0192 mm²).

The objective of this research is to explore circuit techniques and architectures suitable for implementation in digital technologies, that can be used to enhance the efficiency of power stages. Specifically, the use of switching power stages with pulse-width modulation techniques is considered. Switching power stages, such as Class D amplifiers, are inherently well-suited for implementation in deep-submicron CMOS. Pulse-width modulation (PWM) employs discrete amplitude levels and encodes signal information in local time-based averages, and as such can also benefit from such technologies. Additionally PWM does not suffer from quantization noise, and is well-suited for low noise applications. PWM designs, that can be applied for a range of signal bandwidth requirements, spanning several tens to hundreds of kHz are proposed. Applications for these architectures include audio systems, powerline communications and wireless communications. Design challenges and requirements that can arise in different application contexts are considered in the specification of the architectures. A common goal in the definition of the architectures is to minimize complexity of the designs. In the first part of the dissertation, a third-order self-oscillating PWM class-D amplifier for audio applications, that utilizes a hysteretic comparator is described. The design is analyzed and its THD is theoretically determined by employing an equivalent model, that relates the approach to natural sampling pulse-width modulation. The architecture eliminates the requirement for a high-quality carrier generator. A low-cost hysteresis compensation technique is utilized to enhance distortion performance at high output power levels. An implementation is presented in a 0.7um CMOS process. The design achieves a dynamic range (DR) of 116.5 dB, and a THD+N of 0.0012%, while delivering a power of 125 mW into an 8[Omega] load at 1 kHz. The THD+N is under 0.006% up to 90% of the maximum output power. The amplifier can deliver 1.45 W into the load with a THD of 5% with a 5 V power supply. The efficiency is greater than 84% for output power larger than 1 W. The area of the amplifier is 6 mm². The achieved performance indicates that the design is well-suited for high-performance audio applications. A class D line driver that utilizes a phase-locked loop (PLL) based PWM generation technique is presented next. The principle of operation, and implementation details relating to loop stability, linearity and noise performance are analyzed. An implementation is presented in a 130nm CMOS process. The amplifier can deliver 1.2 W into an 6.8[Omega] load with a 4.8 V power supply. The architecture eliminates the requirement for a high-quality carrier generator and a fast, continuous voltage comparator that are often required in PWM implementations. The design can achieve a THD of -65 dB, with a switching frequency that can be as high as 20 MHz. The peak efficiency is 83% for output power larger than 1 W, for a switching frequency of 10 MHz. The area of the amplifier is 2.25 mm². This architecture is potentially suitable for powerline applications. Finally, a phase-locked loop based PWM Cartesian transmitter with the capability to drive switched power amplifiers, such as a Class D power amplifier, is proposed. A phase-locked loop based technique is employed to generate a high-frequency PWM pulse stream centered at 1.28 GHz. The prototype is simulated in a 130 nm CMOS process, and achieves 35% peak efficiency for 17 dBm output power with a carrier frequency of 900 MHz. Operation of the architecture with non-constant envelope modulation, such as that employed in the WCDMA standard, is verified in simulation.

Abstract: Line current distortion is an important issue to a high-power current source rectifier(CSR) system. There are two main challenges related to this issue. First, the CSR input LC resonance can be affected by the variation of the source inductance from the power system and the effects of the CSR DC side circuit, which may lead to a line current distortion higher than expected. Another challenge is that the traditional high-power CSR using Selective Harmonic Elimination (SHE) pulse-width modulation (PWM) technique attempts to eliminate certain harmonics in the PWM current, which limits its ability for line current harmonic control. To control the CSR line current harmonics, this thesis focuses on two aspects: 1) the analysis and design of CSR input filter to avoid unexpected input LC resonance, and 2) the development of a new PWM scheme that can compensate the effects of the grid voltage harmonics and DC link current ripples. The thesis work has been validated by simulations and on an experimental CSR prototype.

Modern electronics are operating at lower voltages with higher currents, requiringpower converters to deliver these requirements efficiently. In this thesis, a switch-inductor buck converter is designed for the required specifications; and for the selecteddesign, component losses and efficiency are calculated. A MATLAB/Simulink modelis constructed, and tested in the presence of load and source disturbances to showthe converter cannot maintain the desired output voltage when the disturbances areapplied.A fuzzy logic PID controller is designed to regulate the duty cycle of the converter tocontrol the output voltage. Control surfaces are designed for proportional, integral,and derivative gains of the fuzzy PID controller. The compensated power converter istested using the Simulink model in the presence of the disturbances, and it is shownthat the fuzzy controller is capable of keeping the power converter output voltagewithin the operating requirements, while improving system speed and stability.

Pulse-width modulation (PWM) is well established in power electronics as a basis for inverters with sinusoidal output voltages. It provides two crucial advantages: high power delivery efficiency and easy digital-to-analog demodulation. Thus PWM can be applied in audio signal processing chain as a switching function for a bridge inverter, and a low-pass filter extracts the audio. Meanwhile, this process is nonlinear. So it has often been assumed that implementation of PWM in audio benefited us with its efficiency improvement at the price of distortion. This work explored how PWM can be applied to provide high fidelity audio signal processing with nonlinearity compensation. The distortion effects are analyzed in depth. Noise-shaping processes that reduce quantization errors in the process are described. An inverter is presented that processes information directly in digital form PWM sequence with accurate correction added in the front end noise shaping module. The signal processing chain from digital input to the inverter gate drives is entirely digital. Simulation results confirm that a PWM inverter with efficient nonlinearity compensation can achieve high fidelity in practice.