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This research details the development of a cutting-edge Low Noise Amplifier (LNA) using advanced 28nm CMOS technology. The study focuses on achieving optimal performance in high-frequency wireless communication systems. The LNA design showcases a significant gain of 40.39 dB at 6.31 GHz and an impressive noise figure of 6.68 dB at 6.31 GHz. The total area of the chip is 0.576 mm2. The methodology includes utilizing a common-stage LNA configuration with inductive source degeneration and cascade structures to enhance gain and noise performance. Special emphasis is placed on impedance matching, with a meticulous design of input and output networks to minimize signal loss and noise addition. The paper also explores key aspects of LNA design, such as transistor sizing, stability, and linearity. Stability is rigorously analyzed using S-parameters, ensuring the LNA's resistance to self-oscillations. Linearity is addressed through measures like the Third-Order Intercept Point (IIP3), ensuring signal integrity in the presence of strong interfering signals.