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This paper presents a wideband low-spur phase-locked loop (PLL) in a standard 90-nm CMOS process. A simple but effective calibration technique is used to reduce the current mismatch of the charge-pump and achieve low reference spurs. The calibration is based on the successive-approximation- register (SAR) control in conjunction with the pulse-width scaling technique to enlarge the current mismatch for a better calibration resolution. The operation frequency range of the microwave PLL covers from 39.5 to 47.1 GHz. The measured phase noise and reference spurs are −92 dBc/Hz at 1-MHz offset and −57.63 dBc, respectively.

This paper presents a 0.18-µm complementary metal-oxide-semiconductor wideband phase-locked loop with low reference spurs. The dual-level charge-pump current calibration technique is proposed to maintain a constant loop bandwidth for wide operation frequency range and achieve low reference spurs. The first level charge-pump current calibration is seamlessly incorporated in the automatic frequency band hopping control and the mechanism also ensures enough negative transconductance for the voltage-controlled oscillator to function throughout the whole frequency range. The charge-pump current mismatch is calibrated by the second level charge-pump current calibration combined with the pulse-width scaling technique. The operation frequency range of the phase-locked loop covers from 4.7GHz to 6.1GHz. The measured phase noise is-116dBc/Hz at 1-MHz offset and the reference spurs are below-66.8dBc. Copyright © 2015 John Wiley & Sons, Ltd.

This paper presents a compact 0.18-?m CMOS wideband gain-flattened low noise amplifier (LNA). The low noise characteristic of the LNA is achieved by the noise canceling technique and the gain flatness is enhanced by the gate-inductive gain-peaking technique. In addition to extending flat-gain bandwidth, the proposed gain-peaking technique results in better wideband noise canceling and quick gain roll-off outside the desired signal band to reject interference. Without using any passive inductor, the core size of the fully-integrated CMOS LNA circuit is only 145 ? m × 247 ? m. The measured gain and noise figure of the CMOS LNA are 16.4 dB and 2.1 dB, respectively. The gain variation of the LNA is ±0.4 dB from 50 to 900 MHz. Operated at 1.8 V, the chip consumes 14.4 mW of power.

This paper presents an amplitude-shift-keying (ASK) demodulator for RF identification tags, which can be embedded on panel displays. The ASK demodulator was implemented in 3-mum low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) technology. Since the threshold voltages of LTPS TFTs are higher than CMOS transistors, the conventional demodulator implementation will degrade the demodulator sensitivity significantly. The novel full-wave demodulator circuit was proposed to resolve the issue of high threshold voltage and reduce the ripples of the demodulated envelope. Operated at 8 V, the demodulator consumes 1.6 mW of power. The input carrier frequency was tested up to 13.56 MHz, and the highest ASK modulated data rate is 100 kb/s. The circuit size of the LTPS TFT demodulator is 500 mum times 450 mum.

This letter presents a 0.18 μm CMOS dual-band frequency synthesizer with charge-pump current mismatch calibration to reduce reference spurs. To enhance calibration accuracy the high-resolution phase detector (HRPD) is incorporated in this work. The measured output spur level is less than -63 dBc after the calibration circuits are activated and the reference spur reduction is more than 5.6 dB throughout the whole frequency range. The frequency synthesizer draws 16 mA from a 1.8 V power supply, and the covered frequency bands are 5.18-5.32 GHz and 5.74-5.82 GHz.

This letter presents a wideband low noise amplifier (LNA) implemented in 0.15 μm InGaAs pHEMT technology. The forward combining technique is proposed to boost the amplifier gain at Ka band. Through gain enhancement, the noise characteristic of the amplifier can also be reduced. The Ka-band LNA exhibits a very wide 3 dB bandwidth from 29 to 44 GHz with the power gain of 14.2 dB. The measured noise figure varies between 2.0 and 3.3 dB from 26.5 to 40 GHz. The supply voltage of the circuit is 1.2 V and the power consumption is 38 mW. The overall chip size is 650 μm×720 μm.

This letter presents the first RF frequency divider on glass to demonstrate the feasibility of system on display (SoD). The frequency divider is developed in 1P2M 3 mum low-temperature polycrystalline silicon (LTPS) thin-film transistor technology. The core cell of the LTPS direct injection-locked frequency divider is the single stage ring oscillator. The additional cross-coupled transistor pair increases the phase shift of the ring oscillator to meet the oscillation condition. The maximum locking range of the LTPS frequency divider is 2 MHz, and it can be operated from 120 Hz to 8 MHz with frequency tuning. Operated at 10 V, the frequency divider consumes 1.8 mW of power. The area of the frequency divider circuitry is 2.13 times 2.6 mm.

This paper presents the design of a low-power ultra-wideband low noise amplifier in 0.18-mum CMOS technology. The inductive degeneration is applied to the conventional distributed amplifier design to reduce the broadband noise figure under low power operation condition. A common-source amplifier is cascaded to the distributed amplifier to improve the gain at high frequency and extend the bandwidth. Operated at 0.6V, the integrated UWB CMOS LNA consumes 7mW. The measured gain of the LNA is 10dB with the bandwidth from 2.7 to 9.1GHz. The input and output return loss is more than 10dB. The noise figure of the LNA varies from 3.8 to 6.9dB, with the average noise figure of 4.65dB. The low power consumption of this work leads to the excellent figure of gain-bandwidth product (GBP) per milliwatt

The low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) is an emerging technology to manufacture active matrix liquid crystal displays. With the TFT's maximum frequency of oscillation fmax exceeding 3.5 GHz, it becomes feasible to develop integrated circuits (ICs) in LTPS TFT technology to facilitate system on panel or system on display. This paper investigates the LTPS TFT characteristics for developing RF ICs. The dc and ac equivalent-circuit models were developed for LTPS TFT RF integrated-circuit design. A phase-locked loop (PLL) was demonstrated using the 3-μm LTPS TFT technology. The supply voltage and power consumption of the PLL are 8.4 V and 25 mW, respectively. The operation frequency range of the TFT PLL is from 2 to 10 MHz, and the measured root-mean-square jitter is 235 ps.

Low temperature polycrystalline silicon (LTPS) thin film transistor (TFT) is an emerging technology to manufacture active matrix liquid crystal displays (AMLCDs). With its maximum frequency of oscillation f max reaching beyond 1 GHz, it becomes feasible to develop integrated circuits in LTPS TFT technology to facilitate system on panel or system on display. This paper investigates the LTPS TFT characteristics for developing RFID tags. An equivalent circuit model was proposed for LTPS TFT RFIC design. An ASK demodulator for the RFID tag was demonstrated using 3µm LTPS TFT technology. The demodulator can operate at the carrier frequency of 13.56 MHz and the highest data rate is 100 kb/s.

This paper presents a IV 0.13 mum CMOS low-power low-noise up-converter for the E2-L1- El/L5-E5a dual-band GPS/Galileo dual-mode receivers. The up-converter includes a low noise amplifier with an embedded image rejection filter (IRF), a mixer and a phase-locked LO source.

To achieve high level of integration and reduce bill of material (BOM), direct down- conversion architecture has become popular for RF receivers. In spite of many associated benefits, direct conversion receivers (DCR) suffer from signal-to-noise ratio (SNR) degradation because of DC offset. This paper proposed the cascaded even-harmonic mixer architecture to reduce the supply voltage requirement. Operated at 1 V, the 0.18-mum CMOS even-harmonic mixer consumes only 1.4 mW and achieves 3-dB conversion gain. The measured LO-to-IF and LO-to-RF isolations are 44 dB and 58 dB, respectively.

This paper presents a low power wide tuning range 0.18 mum CMOS voltage-controlled oscillator. The VCO is oscillating at 1.5 times of the LO frequency to reduce the size of tank inductor. Capacitor bank switching is adopted to increase the VCO tuning range. To ensure oscillation at low frequency band, the bias current is adjusted automatically with respect to oscillation frequency. The frequency coverage of the CMOS VCO is from 675 MHz to 1275 MHz, and the tuning range is 62%. The operation supply voltage and power consumption of the VCO are 1V and 5 mW, respectively. The measured phase noise is - 98 dBc/Hz at 100 kHz offset.

This paper presents a novel low power 0.18 mum CMOS even-harmonic mixer for digital TV (DTV) receivers. The proposed mixer topology can reduce the supply voltage required for the traditional stack topology to achieve low power operation. Operated at 1.8 V, the mixer consumes 2.6 mW of power. Without using integrated inductor for performance enhancement, the core mixer circuit occupies only 0.136 mm2. The measured conversion gain and IIP3 are better than -4 dB and -1.3 dBm, respectively, from 450 MHz to 900 MHz. The LO-to-RF isolation is better than 58 dB.

This paper presents a wide operation range 0.18/spl mu/m CMOS frequency divider for 60GHz wireless applications. The direct injection lock technique is used to perform the signal division at millimeter-wave frequency. The deep n-well is implemented under the NMOS switch transistor to improve the lock range of the frequency divider. Combined with band switching and analog frequency tuning, the operation range of the frequency divider covers from 43 to 49 GHz. Operated at 1V, the frequency divider consumes 8mW of power. The core circuit of the frequency divider occupies 200/spl mu/m /spl times/ 320/spl mu/m of silicon estate.