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In the logic synthesis stage, structure transformations in the synthesis tool need to be combined into optimization sequences and act on the circuit to meet the specified circuit area and delay. However, logic synthesis optimization sequences are time-consuming to run, and predicting the quality of the results (QoR) against the synthesis optimization sequence for a circuit can help engineers find a better optimization sequence faster. In this work, we propose a deep learning method to predict the QoR of unseen circuit-optimization sequences pairs. Specifically, the structure transformations are translated into vectors by embedding methods and advanced natural language processing (NLP) technology (Transformer) is used to extract the features of the optimization sequences. In addition, to enable the prediction process of the model to be generalized from circuit to circuit, the graph representation of the circuit is represented as an adjacency matrix and a feature matrix. Graph neural networks(GNN) are used to extract the structural features of the circuits. For this problem, the Transformer and three typical GNNs are used. Furthermore, the Transformer and GNNs are adopted as a joint learning policy for the QoR prediction of the unseen circuit-optimization sequences. The methods resulting from the combination of Transformer and GNNs are benchmarked. The experimental results show that the joint learning of Transformer and GraphSage gives the best results. The Mean Absolute Error (MAE) of the predicted result is 0.412.

Typical operators for the decomposition of Boolean functions in state-of-the-art algorithms are AND, exclusive-OR (XOR), and a 2-to-1 multiplexer (MUX). We propose a logic decomposition algorithm that uses the majority-of-three (MAJ) operation. Such decomposition can extend the capabilities of current logic decomposition, but only found limited attention in previous work. Our algorithm makes use of a decomposition rule based on MAJ. Combined with disjoint-support decomposition, the algorithm can factorize XOR-Majority Graphs (XMGs), a recently proposed data structure which has XOR, MAJ, and inverters as only logic primitives. XMGs have been applied in various applications, including (i) exact synthesis aware rewriting, (ii) pre-optimization for 6-LUT mapping, and (iii) synthesis of quantum networks. An experimental evaluation shows that our algorithm leads to better XMGs compared to state-of-the-art algorithms, which positively affect all these three applications. As one example, our experiments show that the proposed method achieves up to 37.1% with an average of 9.6% reduction on the look-up tables (LUT) size/depth product applied to the EPFL arithmetic benchmarks after technology mapping.

Using state assignment to minimize power dissipation and area for finite state machines is computationally hard. Most of published results show that the reduction of switching activity often trades with area penalty. In this paper, a new approach is proposed. Experimental results show a significant reduction of switching activity without area penalty compared with previous publications.

3-input AND/XOR is the basic complex gate of Reed-Muller logic. Low energy consumption is important for Reed-Muller logic circuit implementation. Against the drawbacks of the published gate-level and transistor-level 3-input AND/XOR gate design in power and power delay product (PDP), a low energy consumption 3-input AND/XOR gate is proposed by employing multi-rails and hybrid-CMOS techniques to improve its speed and short the signal transimission path. Under 55nm CMOS process, post-simulations in different process corners are carried out by using HSPICE and compared with the published circuits. Simulation results show that the proposed circuit has advantages over published designs. For typical process corners, the improvement of the proposed circuit can be up to 27.21%, 19.23% and 35.39%, respectively, in terms of power, delay and power delay product.

The digital-to-analogue converter (DAC) plays a significant role in modern electronic systems, and current-mode DACs are widely used due to their excellent properties. However, the non-ideal transition at switching instants of the unit circuit will directly affect the performance of the current-mode DAC. The parasitic effects resulting in non-ideal transition are analyzed in this paper. A simple structure unit circuit is proposed to diminish the non-ideal transition. The simulation results show that the parasitic effects are suppressed effectively, and a smoother output transition is achieved. The feasibility of the proposed current-mode DAC unit circuit is verified by the application in a frequency jitter circuit.

With the rapid increase in the density and the size of chips and systems, area and power dissipationbecome critical concern in Very Large Scale Integrated (VLSI) circuit design. Low powerdesign techniques are essential for today's VLSI industry. The history of symbolic logic and sometypical techniques for finite state machine (FSM) logic synthesis are reviewed.The state assignment is used to optimize area and power dissipation for FSMs. Two costfunctions, targeting area and power, are presented. The Genetic Algorithm (GA) is used to searchfor a good state assignment to minimize the cost functions. The algorithm has been implementedin C. The program can produce better results than NOVA, which is integrated into SIS by DCBerkeley, and other publications both in area and power tested by MCNC benchmarks.Flip-flops are the core components of FSMs. The reduction of power dissipation from flip-flopscan save power for digital systems significantly. Three new kinds of flip-flops, called differentialCMOS single edge-triggered flip-flop with clock gating, double edge-triggered and multiple valuedflip-flops employing multiple valued clocks, are proposed. All circuits are simulated using PSpice.Most researchers have focused on developing low-power techniques in AND/OR or NAND& NOR based circuits. The low power techniques for AND /XOR based circuits are still intheir early stage of development. To implement a complex function involving many inputs,a form of decomposition into smaller subfunctions is required such that the subfunctions fitinto the primitive elements to be used in the implementation. Best polarity based XOR gatedecomposition technique has been developed, which targets low power using Huffman algorithm.Compared to the published results, the proposed method shows considerable improvement inpower dissipation. Further, Boolean functions can be expressed by Fixed Polarity Reed-Muller(FPRM) forms. Based on polarity transformation, an algorithm is developed and implementedin C language which can find the best polarity for power and area optimization. Benchmarkexamples of up to 21 inputs run on a personal computer are given.