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2. Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to lOnm and 30nm gate length

Author

Collaert, N., Von Arnim, K., Rooyackers, R., Vandeweyer, T., Mercha, A., Parvais, B., Witters, L., Nackaerts, A., Sanchez, E. Altamirano, Demand, M., Hikavyy, A., Demuynck, S., Devriendt, K., Bauer, F., Ferain, I., Veloso, A., De Meyer, K., Biesemans, S., Jurczak, M., Laboratorium for Micro- and Photonelectronics, Electronics and Informatics, Faculty of Economic and Social Sciences and Solvay Business School, Faculty of Medicine and Pharmacy, and Chemical Engineering and Industrial Chemistry

Subjects
Hardware_MEMORYSTRUCTURES, SOI FinFET, human-computer interaction, Ring oscillators, Hardware_INTEGRATEDCIRCUITS, Hardware_PERFORMANCEANDRELIABILITY, Electrical and Electronic Engineering, SRAM
Abstract

While the potential of FinFETs for large-scale integration (LSI) was demonstrated before on relaxed device dimensions, in this paper we present performance data of aggressively scaled transistors, ring oscillators and SRAM cells. FinFET SRAMs are shown to have excellent VDD scalability (SNM-185mV at 0.6V), enabling sub-32nm low-voltage design.

Published
2008

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