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Hybrid integration of III-V materials onto silicon by direct bonding technique is a mature and promising approaches to develop advanced photonic integrated devices into the silicon photonics platform. In this approach, the III-V material stack is grown on an InP wafer in a unique epitaxial step prior to the direct bonding process onto the silicon-on-insulator wafer. Currently, no additional epitaxial regrowth steps are implemented after bonding. This can be seen as a huge limitation as compared to the III-V on III-V wafer mature technology where multi-regrowth steps are most often implemented. In this work, we have studied the material behavior of an InP membrane on silicon (InPoSi) under epitaxial regrowth conditions by metal-organic vapor phase epitaxy (MOVPE). MOVPE requires high-temperature elevation, typically above 600 °C. We show for the first time the appearance of voids at 400 °C in an InP seed (100 nm) directly-bonded onto a thermally oxidized Si substrate despite the use of a thick SiO2 oxide (200 nm) at the bonding interface. This phenomenon is explained by a weakening of the bonding interface while high-pressurized hydrogen is present. A kinetic study of the hydrogen lateral diffusion is carried out, enabling the assessment of its lateral diffusion length. To overcome the void formation, highly efficient outgassing trenches after bonding are demonstrated. Finally, high-quality AlGaInAs-based multi-quantum well (MQW) heterostructure surrounded by two InP layers was grown by MOVPE on InPoSi template patterned with outgassing trenches. This process is not only compatible with MOVPE regrowth conditions (650 °C under PH3) but also with conventional fabrication processes used for photonic devices.

This paper presents an eight-channel optical transmitter and receiver circuit fabricated in 0.35 µm SiGe BiCMOS and integrated via inter-wafer connections to a photonic circuit fabricated in 220 nm SOI photonic technology in a 200 mm CMOS foundry. Measurement results demonstrate 8×l Gb/s for transmitter and 8×10 Gb/s for the receiver. The transmitter's extinction ratio is 5 dB. The receiver shows a sensitivity of −8.5 dBm at 10 Gb/s and a BER of 10–9, with a significant margin for improvement by optimizing the grating coupler efficiency, by a better fiber coupling, and to a lower extent by better matching the output impedance of the circuit.

EUV lithography is expected to be inserted for the 32 nm node and extended for the 22 nm and below. Phase shift masks (PSM) are evaluated as a possible option to push the resolution limit of the Extreme Ultra violet lithography. This paper will focus on designs and measurements of PSM implemented by etching into the Mo/Si multilayer (ML). The design and the technological developments to elaborate PSM by etching is described. Phase shift Sample (PSS) have been carried out to calibrate in "true operating conditions", i.e. through the measurement of the phase shift they produce on a reflected wavefront, at the wavelength (λ=13.5nm). The method of calibration have been investigated with a Fresnel bimirror interferometer installed on the PSI Swiss Light Source Synchrotron to measure directly the value of interest, i.e the optical phase.

In the field of microelectronics, the Extreme Ultraviolet (EUV) lithography operating at λ=13,5 nm, appears, today, as the most promising future technology. The viability of this next generation technology has, however, to face several technical issues. Among them, the realisation of highly reflective EUV mirrors is one of the key issues and concerns the mirrors for light transport as well as the lithography masks. In this last case, the mirrors which consist in a periodic Mo/Si multi-layer coating deposited by ion beam sputtering suffer from reflectance limitations and thermal instabilities. In this paper, an experimental investigation on IBS deposited Mo/Si multi-layers is presented. The study is mainly focused on the formation of Mo/Si interfacial zones and their evolution with thermal annealing up to 600°C. Detailed investigations by high-resolution transmission electron microscopy (HRTEM) and energy filtering TEM have been performed in association with differential scanning calorimetric (DSC) analyses. For the purpose, dedicated samples were prepared enabling the identification of phase transformations occurring during thermal annealing. It will be shown, in particular, how this coupled characterisation approach (TEM+DSC) can help understanding the interface growth in such metal/silicon systems. The characterisation results are presented and discussed.

In this paper, defect counting results are presented both on silicon substrates and on EUV mask blanks with their equivalent PSL size distribution. The measurements are achieved with our counting defect prototype COMNET but also with a commercial tool. Improvements of COMNET have been performed to reach sensitivities (PSL equivalent size on silicon) of 80 nm on silicon substrate, 90 nm on EUV mask blank and 125 nm on glass substrate. A first analysis about COMNET repeatability is presented and the impacts of known errors on defect number and size values are evaluated. Typical counting data measured on a EUV mask blank having an added defect density inferior to 1 def/cm2 (defect size superior to 90 nm) are presented. The analysis of these data shows two main populations of added defects which are characteristic of the deposition process: one close to 100 nm and the other in the micron range. Each group represents half of the total number of added defects. The origins of these defects are finally discussed on the basis of specific experiments chosen to highlight the possible role of the different process steps.

Copper nanoparticles (NPs) were synthesized by inert-gas condensation of a sputtered metallic vapor using a dedicated commercial reactor. By controlling the time of residence of NPs in the carrier gas phase via the tuning of the collision path length, Cu NPs were produced. They exhibit various and well controlled diameters (3–10 nm) and a relatively narrow size dispersion. On the basis of these experimental results, a detailed modeling of NP nucleation and growth based on the classical nucleation theory was developed. It takes into account the peculiar geometry and thermal profile of the NP reactor. The simulated curves, calculated by a MATLAB® program developed for that purpose, exhibit a good qualitative agreement with experiment. Moreover, they highlight the role of process parameters and the strong influence of the reactor temperature profile on the NP size distribution. In the future, such calculations could be used for the optimization of the NP source design in order to increase its efficiency and ...