Search

The intrinsic characteristics of novel devices and materials are often misunderstood due to the characterization methods which are developed to analyze existing devices or materials. Even though graphene is a very well-known material, there hasn't been a proper method to assess the density and energy levels of defects in graphene non-destructively, especially after the device fabrication. Here, we report a new non-destructive defect analysis method, amplitude-modulated discharge current analysis (AMDCA). The validity of this method was confirmed using a graphene field effect transistor with physically predefined defect densities in the channel. Charge trap densities ( N c t ) of the order of ∼1012 cm−2 were observed at the defect level in the range of 0.15–0.29 eV. This method can be very useful for the in-depth study of graphene devices as well as other two-dimensional materials that don't have a body contact.

Barrier height ( $\phi _{b}$ ), trap state, bandgap ( $E_{g}$ ), and band alignment information of the metal–ZrO2–metal capacitor have been extracted using internal photoemission (IPE) system. By correlating the IPE analysis with I-V and C-V characteristics obtained before and after rapid thermal annealing, origin and transformation of defect states have been successfully investigated. Our analysis revealed that deep-level defects originating from oxygen vacancies near the top electrode are causing of leakage current in MIM capacitor and these defects can be effectively reduced by a proper thermal annealing.

Barrier height ( $\phi _{b}$ ), trap state, bandgap ( $E_{g}$ ), and band alignment information of the metal–ZrO2–metal capacitor have been extracted using internal photoemission (IPE) system. By correlating the IPE analysis with I-V and C-V characteristics obtained before and after rapid thermal annealing, origin and transformation of defect states have been successfully investigated. Our analysis revealed that deep-level defects originating from oxygen vacancies near the top electrode are causing of leakage current in MIM capacitor and these defects can be effectively reduced by a proper thermal annealing.

A two-dimensional (2D) WOx/ZnO stack reveals a unique carrier transport behavior, which can be utilized as a novel device element to achieve a very high on/off ratio (>106) and an off current density lower than 1 nA cm−2. These unique behaviors are explained by a dynamic band alignment between WOx and ZnO, which can be actively modulated by a gate bias. The performance of FET utilizing the WOx/ZnO stack is comparable to those of other 2D heterojunction devices; however, it has a unique benefit in terms of process integration because of very low temperature process capability (T < 110 °C). The high on/off switching with extremely low off current density utilizing the dynamic band alignment modulation at the WOx/ZnO stack can be a very useful element for future device applications, especially in monolithic 3D integration or flexible electronics.

A quantum confined transport based on a zinc oxide composite nanolayer that has conducting states with mobility edge quantization is proposed and was applied to develop multi-value logic transistors with stable intermediate states. A composite nanolayer with zinc oxide quantum dots embedded in amorphous zinc oxide domains generated quantized conducting states at the mobility edge, which we refer to as “mobility edge quantization”. The unique quantized conducting state effectively restricted the occupied number of carriers due to its low density of states, which enable current saturation. Multi-value logic transistors were realized by applying a hybrid superlattice consisting of zinc oxide composite nanolayers and organic barriers as channels in the transistor. The superlattice channels produced multiple states due to current saturation of the quantized conducting state in the composite nanolayers. Our multi-value transistors exhibited excellent performance characteristics, stable and reliable operation with no current fluctuation, and adjustable multi-level states., Designing multi-value logic transistors with stable and reliable intermediate states remains a challenge. Here, the authors report the mobility edge quantization phenomenon via resonant hybridization of ZnO QDs embedded in amorphous ZnO domains to enable adjustable multi-value intermediate states.

A two-dimensional (2D) WO

Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of ~10−16 J, which is comparable to the binary equivalent circuit. The ternary full adder was modeled using device parameters extracted from the experimentally demonstrated multi-Vth ternary graphene barristors.

A graphitic capping layer was successfully formed on top of Cu interconnects at room temperature, using a pulsed KrF laser. The change in temperature of the Cu line was maintained below 380 °C during laser irradiation with a fluence of 312.5 mJ/cm2. The resistance and critical current density of graphitic layer-capped Cu interconnects were improved by 2.8% and 5.2%, respectively. The lifetime of graphitic layer-capped Cu interconnects under a constant current stress was improved by 223%.

The capacitor dielectric dispersion characteristic has become an important design parameter, because the effective dielectric constant of a high-k dielectric significantly changes at high frequencies. However, current methods for capacitance measurement have limitations in the measurement range or the test complexity. In this letter, a new method to measure the dispersion characteristics at a wider frequency region was demonstrated using time-domain reflectometry. Using this method, the dispersion characteristics can be obtained from 200 kHz to 70 MHz without using any complex test structure or compensation procedure.

Graphene barristors with two parallel connected n-type and undoped graphene channels are used to build a ternary logic switch. Three distinctly separated out current levels are successfully demonstrated and the experimental device parameters obtained from the graphene barristor based ternary switch are used to model the ternary circuit modules. Well-behaving standard ternary inverter, NMIN, NMAX, and ternary comparator have been obtained, confirming the feasibility of large scale integration of ternary logic devices.

We propose a simple method to monitor the quality of MIM capacitor. The differences in the slope of C-F curve at low and high frequency are found to be a good indicator showing the difference in the reliability characteristics of MIM capacitor. Asymmetric interface trap generation near top or bottom electrode could be monitored and clear difference was observed at various dielectric thickness, measurement temperature and stack structures.

High-pressure annealing in oxygen ambient at low temperatures (∼300 °C) was effective in improving the performance of graphene field-effect transistors. The field-effect mobility was improved by 45% and 83% for holes and electrons, respectively. The improvement in the quality of Al

Novel thin film transistor based on a graphene-ZnO Schottky junction has been demonstrated for display driver circuit applications. High transmittance over 80% in visible light wavelengths with a high on-off ratio over 104 are the merits of this device. All device fabrication processes completed at a temperature below 200°C will provide a unique advantage in the flexible display applications. The projected performance estimated by PSPICE using the experimental device parameters confirmed that this device is suitable for voltage programming pixel driver circuits.

Tunable DC voltage control circuit based on a half-wave rectifier was developed using a graphene–germanium barristor. The output DC voltage level could be modulated at 30–100% of the peak voltage by controlling the Schottky barrier height between graphene and germanium using a gate bias. Owing to the simple and low-temperature integration process, this device can be used for a variable DC power supply in monolithically integrated circuits or flexible devices.

Graphene field effect transistors (GFETs) with top-gate and back-gate structures have been extensively used without much consideration for compatibility with graphene. A comparative study of the electrical characteristics of buried-gate GFETs and top-gate GFETs revealed that the performance of buried-gate GFETs is drastically enhanced by having a better gate controllability, achieving three times higher field effect mobility (~3000 cmlsupg2l/supg/Vs) than top-gate GFETs with on/off ratio ~10.Carrier scattering was also substantially improved by minimizing the fringing field effect, which is found to be the origin of high series resistance in top-gate GFETs. Moreover, we showed by electromagnetic (EM) simulation that the electric field distribution inside the transistors is more uniform at the buried-gate GFETs than the top-gate GFETs.

This study proposes a design of a ternary logic inverter using graphene barristor (GB). To design a multiplevalued logic gate, controlling threshold voltages of the unit device should be easy. We determined that the doping concentration of the graphene can easily control the operation voltage of the GB. To realize an ideal ternary logic gate, the concept of a single pole triple throw switch is proposed and designed using the GB. The designed ratioless GB ternary inverter was simulated using SPICE and Mathematica. Voltage transfer characteristics of the proposed ternary invertershowed sharp ternary characteristics and its static power consumption was nearly zero.

Various photodetectors showing extremely high photoresponsivity have been frequently reported, but many of these photodetectors could not avoid the simultaneous amplification of dark current. A gate-controlled graphene-silicon Schottky junction photodetector that exhibits a high on/off photoswitching ratio (≈104 ), a very high photoresponsivity (≈70 A W-1 ), and a low dark current in the order of µA cm-2 in a wide wavelength range (395-850 nm) is demonstrated. The photoresponsivity is ≈100 times higher than that of existing commercial photodetectors, and 7000 times higher than that of graphene-field-effect transistor-based photodetectors, while the dark current is similar to or lower than that of commercial photodetectors. This result can be explained by a unique gain mechanism originating from the difference in carrier transport characteristics of silicon and graphene.

High-pressure annealing in oxygen ambient at low temperatures (∼300 °C) was effective in improving the performance of graphene field-effect transistors. The field-effect mobility was improved by 45% and 83% for holes and electrons, respectively. The improvement in the quality of Al2O3 and the reduction in oxygen-related charge generation at the Al2O3-graphene interface, are suggested as the reasons for this improvement. This process can be useful for the commercial implementation of graphene-based electronic devices.

Graphene–ZnO:N Schottky junction barristors are fabricated on a flexible polyethylene naphthalate substrate utilizing a low thermal budget integration process with a maximum process temperature below 200 °C. An on/off ratio of over 104 is obtained with a 0.1 A/cm2 drive current density at Vd = 0.5 V. The transmittance, degraded by the device stack, was 2.5–3% in the visible wavelength range, and a high on/off ratio was maintained after 600 bending cycles at a 0.6% strain (bending radius = 10 mm).