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This paper describes a systematic approach to design FPGA package for current carrying capability. As we examine silicon, interposer, and package, the profound challenge is found to meet the lifetime of high power device against the greater chance of failures owing to worsen electro-migration in every interconnect level. Our approach consists of practical methodologies to estimate current distribution and to calculate accumulated failure rates from an entire substrate including BGA ball, micro-via and plated through hole. The approach reported here allows lifetime calculation from the progressive failure of individual BGA over the different time span. In the end, we apply the methodology to a 200A high power design achieved with the most efficient ball count that meets lifetime specification.

Jitter margin loss as result of crosstalk impairment emerges as increasing challenge at 28Gbps and beyond. As silicon compensation is known ineffective to crosstalk, package becomes critical path of system jitter margin. At this speed, signal coupling needs to be kept at well below -50dB in order to ensure adequate insertion-loss-to-coupling ratio (ICR) for protocol jitter compliance. In this paper, we studied coupling mechanism and design options to achieve -50dB to -70dB coupling for devices used in 28G long reach, mixed long reach, short reach environments. Furthermore, we solved the myth of power-ground co-referencing for high speed transceivers. The investigation is carried out by theoretical analysis, full-wave modeling, link simulation, and hardware measurement validation.

The recent market demand to high power 16nm FPGA has challenged package design to an unprecedented level. Specifically, logic tense applications require significantly greater dynamic current than previous generations. This paper describes recent advancements in high power FPGA package design for current-carrying capability. Firstly, new design methodologies are introduced that can link physical design for optimal current distribution directly to failure rate as a result of electro-migration (EM) in stated lifetime. Secondly, a specific design case is analyzed with the new method to show how BGA pin pattern can impact maximal current carrying capability.

The applications to increasing number of transceivers and data rate require extra ground pins (i.e. BGA balls) reserved for channel isolation and crosstalk control. To improve total pin utilization, a transceiver package often resorts to power pins to replace up to 50% of ground pins. However, power pins can fail providing adequate isolation for transceivers operating at 16Gbps and higher data rate. In this paper, we provide latest study results to the fundamental physics of transceiver crosstalk arising from power pin isolation. The mechanism is validated by modeling and simulation in both signal and power distribution network (PDN) domains. It is demonstrated that PDN resonance is reciprocally proportional to the crosstalk introduced. Most importantly, proper design approach is introduced to ensure power-ground co-referencing to deliver nearly identical performance as all-ground scheme in the 50dBs.

As the FPGA device performance increases and integrated circuit reduces in size there will be more and more challenges on the package design. Detailed analysis to capture and address design challenges is important for a viable power distribution network (PDN) package design. This paper will discuss the modeling methodology to analyze the static voltage drop for the high performance and high density FPGA flip-chip packages. Thru the analysis, the design solution to optimize the IR drop and EM problem will be presented.

With silicon process technology advanced to 20 nm node and beyond, die size is continuously shrinking. Package cost is very sensitive to the total cost of an entire chip/ASIC (Application-Specific Integrated Circuit). To reduce package cost, either the package layer count needs to be reduced or the package size needs to be decreased. For a given chip/ASIC design, its high-speed IO (Input Output) pin numbers are fixed in order to meet a certain functional specification, and associated power pins are optimized to guarantee the IO performance. If some of the power pins can be used as references for high-speed IOs, a same die can sit on a small package or a same package can accommodate a die with more high-speed IO pins, which equivalently results the package cost reduction. This motivates the investigation on power and ground co-reference design for highs-speed IOs not only on the concern of cost reduction but also the design insights. In this paper, a production based package with pure ground as reference is studied. A power and ground co-reference design is formed by changing six ground pins from the production package to power pins in test package. The performance of high-speed IOs is compared between pure ground reference design and the power and ground co-reference design. Discussions and conclusions are followed by the comparison, and further study is proposed at the end of the paper.

Wire bond packaging for semiconductor devices has been the choice of low cost implementation to memory interface and high-speed transceivers. However, accurate characterization for wire bond package remains challenging owing to lack of consistent probing methodology. Meanwhile, semiconductor devices tend to have increasingly higher density of I/O, logic circuits and transceiver circuits yet shrinking die size. Therefore, the bonding die pads have to be allocated ever closer to accommodate more I/Os, transceivers and powers. This has made any 2-port transfer function measurement involving link between die pad through wire to BGA balls next to impossible. In this paper, an innovative measurement technology, surrogate chip substrate is proposed to enable accurate and consistent wire bond package measurements for multiple High Speed Serial Interface (HSSI) channel, Double Data Rate (DDR) interface, and wire bond implementation of Power Distribution Networks (PDN)

This paper presents a crosstalk model base on even-odd mode analysis. It demonstrates that crosstalk analysis needs to look at the aspect of the timing delay between even and odd mode and the multiple reflections that occurred in a system. This concept is validated further by measurement result.

This paper presents the dominant contributors of mutual inductance in wire-bond package thru study on the return path. The study is validated through real device measurement correlation. Based on the study, techniques to reduce crosstalk in wire-bond package will be presented which will be beneficial to the packaging world as bond wire continues to be the dominant technique to connect die to the package in low cost application.

Cu pillar is an emerging interconnect technology which offers many advantages compared to traditional packaging technologies. This paper presents a novel packaging solution with periphery fine pitch Cu pillar bumps for low cost and high performance Field Programmable Gate Array (FPGA) devices. Wire bonding has traditionally been the choice for low cost implementation of memory interfaces and high speed transceivers. Migration to Cu pillar technology is mainly driven by increasing demand for IO density and package small form factor. Cu pillar bumps also offer significant improvement on electrical performance compared to wire bonds. This paper presents Cu pillar implementation in an 11×11mm flip chip CSP package. Package design is optimized for serial data transport up to 6.114Gbps to meet CPRI_LVII and PCIe Gen2 compliance requirements. Package design strategy includes die and package co-design, SI/PI modeling and physical layout optimization.