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Aconitine and hypaconitine are the main active ingredients of Radix Aconiti, paeoniflorin and albiflorin are the primary components of Radix Paeoniae Alba. Both Radix Aconiti and Radix Paeoniae Alba are herbs that are commonly used in traditional Chinese medicine. This study sought to explore the mechanistic transport of aconitine and hypaconitine across MDCK-MDR1 cells and to assess the effect of paeoniflorin and albiflorin on aconitine and hypaconitine transmembrane transport as a potential attenuation mechanism. Drug cytotoxicity was tested via the MTT (3-(4,5-Dimethylthiazol-2-yl)-2,5-diphenyltetrazolium bromide) assay, and transport studies were performed in both directions. The effects of drugs on P-gp ATPase activity, P-gp efflux function, MDR1 mRNA and P-gp expression were evaluated in MDCK-MDR1 cells. Aconitine and hypaconitine treatment with the verapamil could significantly decrease the efflux rate (ER). The ER of aconitine and hypaconitine were significantly increased with the coadministration of paeoniflorin and albiflorin, suggesting that paeoniflorin and albiflorin can promote the efflux of these two alkaloids. Aconitine and hypaconitine can induce P-gp enzymatic activity, inhibit P-gp-mediated efflux, and downregulate the expression of P-gp protein to produce cytotoxic effects. When treatment in combination with paeoniflorin and albiflorin, it could stimulated P-gp ATPase activity, increasing mRNA expression, enhance P-gp efflux function, and upregulate P-gp protein expression.

In today's automotive ICs, online safety checking is often required in order to achieve a high Automotive Safety Integrity Level (ASIL). For a Delay-Locked Loop (DLL), the most important safety (or health) indicator is the “phase error between the input clock signal and the output clock signal”. In this paper, we present a phase error monitoring scheme for DLLs, using circuits made of only standard cells. The proposed scheme can monitor the phase error continuously to record its worst-case values during a designated monitoring session. As a result, hazardous phase error glitches can be exposed and an alarm can be raised. We have implemented this monitoring scheme for a Delay Lock Loop in a 90 nm CMOS process and post-layout simulation is conducted to verify its effectiveness. Experimental results show that it can help expose hazards induced by dynamic power glitches that occurs within 1ns.

This research sought to study the influence and potentialmechanism of paeoniflorin and albiflorin on strychnine and brucine transport in MDCK-MDR1 cells regulated by P-gp. Cytotoxicity of drugs was tested by MTT assay, and the transport studies were performed in both directions in MDCK-MDR1 cells. The influence of drugs on P-gp ATPase, and the efflux function of P-gp, the expression levels of P-gp and MDR1 mRNA were also estimated. Strychnine and brucine showed well absorption, and the main transport mechanism might be passive diffusion. Verapamil could significantly decrease the efflux rate (ER) of strychnine and brucine, while the ER of strychnine and brucine was increased significantly when co-administrated with paeoniflorin or albiflorin, indicating that paeoniflorin and albiflorin could promote the efflux of these two alkaloids. Strychnine and brucine could activate the activity of P-gp ATPase, suppress the efflux function of P-gp, but have no significant effect on the expression of P-gp. In addition, strychnine could upregulate the expression of MDR1 mRNA. Paeoniflorin and albiflorin could increase the transmembrane transport of strychnine and brucine mediated by P-gp when co-administrated with strychnine or brucine via stimulating the activity of P-gp ATPase, enhancing the efflux function of P-g, increasing the expression levels of MDR1 mRNA and P-gp.

Diagnosis of intermittent scan chain failures still remains a hard problem. In this article, we demonstrate that the use of artificial neural networks (ANNs) can lead to significantly higher accuracy. The key of this method is a multistage process incorporating ANNs with gradually refined focuses. During this process, the final fault suspect is elected through multiple rounds of ANN inference, instead of just one round. At each stage, identification of a proper Affine Group , used as the “candidate set of scan cells for the next round of ANN inference,” will influence the final diagnostic accuracy. Thus, we propose a validation-based learning procedure for Affine Group derivation to further boost the final diagnostic accuracy. The experimental results on benchmark circuits have shown that this method is, on the average, 17.46% more accurate than a state-of-the-art commercial tool for intermittent stuck-at-0 faults.

This article proposes an automatic compiler for an on-chip time-to-digital converter (TDC) that can be used for monitoring the on-chip operating conditions such as temperature and supply voltage. The proposed compiler adopts a resilient architecture and supports self-calibration and range adjustment. In addition, a novel technique for fine-shrinking cell analysis is proposed to explore the tradeoffs among area, timing resolution, operating range, etc.

Natural berberine-derived azolyl ethanols as new structural antibacterial agents were designed and synthesized for fighting with dreadful bacterial resistance. Partial target molecules exhibited potent activity against the tested strains, particularly, nitroimidazole derivative

The determination of charged particle trajectories in collisions at the CERN Large Hadron Collider (LHC) is an important but challenging problem, especially in the high interaction density conditions expected during the future high-luminosity phase of the LHC (HL-LHC). Graph neural networks (GNNs) are a type of geometric deep learning algorithm that has successfully been applied to this task by embedding tracker data as a graph -- nodes represent hits, while edges represent possible track segments -- and classifying the edges as true or fake track segments. However, their study in hardware- or software-based trigger applications has been limited due to their large computational cost. In this paper, we introduce an automated translation workflow, integrated into a broader tool called $\texttt{hls4ml}$, for converting GNNs into firmware for field-programmable gate arrays (FPGAs). We use this translation tool to implement GNNs for charged particle tracking, trained using the TrackML challenge dataset, on FPGAs with designs targeting different graph sizes, task complexites, and latency/throughput requirements. This work could enable the inclusion of charged particle tracking GNNs at the trigger level for HL-LHC experiments., Comment: 28 pages, 17 figures, 1 table, published version

Reliability of an electronic device, concerning if it can function reliably over its designated lifetime in the field (such as 10 or 15 years), has become more and more important in today's safety-critical applications such as automotive electronics. Traditionally, the ageing has been performed in an offline setting where stress test has been applied to accelerate the ageing process and then a model is established to make the futuristic prediction. This kind of offline method has a drawback of not being able to take into account the factor of the unique operating condition and environment that a device could have experienced in the field. In this work, we present the first cloud-based ageing monitoring system to the best of our knowledge, for the Internet-of-Things (IoT) devices. It has many advantages. First of all, one can know of the ageing status of an IoT device remotely and continuously. Secondly, through data analysis in a cloud server, more accurate prediction can be achieved. Thirdly, an ageing hazard can be alarmed in advance before it actually strikes, and thereby pre-caution actions (such as online repair, or even call-for-maintenance request) can be taken in advance to avoid unnecessary system fatal failure. A prototype system using test chips with built-in design-for-ageing-monitoring circuitry will be demonstrated with measurement data collected through a cloud server.

In this paper, we present a cell-based delay-locked loop (DLL) with an enhanced continuous tracking range. The main contribution is a novel delay line architecture called ping-pong delay line, making it highly resilient to process and temperature variation. In such a DLL design, two cell-based delay lines are incorporated in a way that they exchange their role of command dynamically like in a ping-pong game, and therefore the joint ping-pong delay line can react to severe environmental changes over a very wide range without disruption to the system's operation. The post-layout simulation using a 90-nm complimentary metal-oxide silicon (CMOS) process technology has demonstrated its advantages. A DLL using such a feature can operate reliably even under an extremely hostile environment when the supply voltage drops from 1 to 0.9 V within a timeframe of 4us.

For a safety-critical IC, on-chip monitors have become more and more necessary to discover run-time performance hazards as soon as possible. The general performance metrics that have been targeted in the literature are numerous, such as, the maximum operating speed of a circuit component, the interconnect delay, the transition time or leaking current at an IO pin, etc. In this short paper, we will briefly summarize the features of some of them related to a clock signal, in particular, the performance monitors for excessive jitters, phase errors, or duty-cycle errors. Even with only mature process technology, e.g., a 90nm CMOS process, fine-resolution monitors with the time resolution of only a few picoseconds can still be easily achieved by cell-based designs.

We present in this paper the first fault and soft error tolerant Delay-Locked Loop (DLL) design, useful for the clock synchronization in a chip incorporating heterogeneous functional dies. In this robust DLL design, we introduce a powerful timing correction scheme to remedy the timing shortfall in a naive Triple-Module Redundancy (TMR) architecture. Post-layout simulation results using a 90nm CMOS process is used to verify the performance of this design. In addition to the tolerance of randomly injected faults or soft errors, the Maximum Phase-Error can be improved tremendously from 117ps to just 17ps by the proposed timing correction scheme.

For a Phase-Locked Loop (PLL), the clock period variation is one important health condition indicator. In this paper, we present a rapid min-MAX period monitoring scheme for PLLs, using circuits made of only standard cells. The proposed scheme can monitor the clock period of a PLL ’s output clock signal continuously during a designated monitoring session, while reporting the minimum and maximum clock periods in a timely manner. As a result, performance hazards can be timely exposed and an alarm can be raised earlier. The most unique contribution in this work is the design of a novel min-MAX Time-to-Digital converter (TDC). We have implemented this monitoring scheme and integrated it with a cell-based PLL in a 90nm CMOS process and post-layout simulation is conducted to verify its effectiveness. Experimental results show that the proposed scheme is able to detect some dangerous conditions when the PLL ’s output clock signal exhibits abnormal clock cycle times due to some online transient fault.

A Phase Detector is an indispensable component in a Delay-Locked Loop (DLL). It compares the phases of two input clock signals and then produce a binary lead/lag signal to indicate which clock signal arrives earlier. The resolution of a PD often determines the accuracy of a DLL in terms of the phase error. Unfortunately, a traditional cell-based PD is strongly susceptible to the process variation. In this paper, we propose a “Voting PD design” to alleviate this problem. First, a number of primitive phase detectors are incorporated, and then their primitive results undergo a majority voting process to produce the final lead/lag signal, and thereby enhancing the overall resolution. A statistical approximation shows that process variation can be compressed to 53% using a voting group of 5 primitive phase detectors.

This paper presents a cell-based 50% Duty-Cycle Correction (DCC) design supporting a super-wide range of clock frequency from 10MHz to 1.2GHz, using a 90nm CMOS process. It can be integrated with a Delay-Locked Loop (DLL) as a convenient post-processing unit while achieving “zero phase shift” in a way that the phase locking result achieved by its precedent DLL is not affected at all. The unique features in this design include: (1) A wide-range and high-resolution Half-Period Tunable Delay Line (HP-TLD), (2) A fast-locking unit to enable our DCC to lock in to a new incoming clock frequency during frequency scaling, and (3) A wide-range and high-resolution Duty-Cycle Judge (DCJ) circuit as a feedback to guide the overall duty-cycle correction process. Post-layout simulation in a 90nm CMOS process is conducted to validate its effectiveness.

Product quality control is a prerequisite for ensuring safety, effectiveness, and stability. However, because of the different strain species and fermentation processes, there was a significant difference in quality. As a result, they should be clearly distinguished in clinical use. Among them, the fermentation process is critical to achieving consistent product quality. This study aims to introduce near-infrared spectroscopy analysis technology into the production process of fermented Cordyceps powder, including strain culture, strain passage, strain fermentation, strain filtration, strain drying, strain pulverizing, and strain mixing. First, high performance liquid chromatography (HPLC) was used to measure the total nucleosides content in the production process of 30 batches of fermented Cordyceps powder, including uracil, uridine, adenine, guanosine, adenosine, and the process stability and interbatch consistency were analyzed with traditional Chinese medicine (TCM) fingerprinting, followed by the near-infrared spectroscopy (NIRS) combined with partial least squares regression (PLSR) to establish a quantitative analysis model of total nucleosides for online process monitoring of fermented Cordyceps powder preparation products. The model parameters indicate that the established model with good robustness and high measurement precision. It further clarifies that the model can be used for online process monitoring of fermented Cordyceps powder preparation products.

A clock network is not only difficult to design, but also challenging to test. For high-performance designs with a rigorous clock-skew requirement, small defects in a clock tree network could lead to unexpected failures in the field and thus need to be identified during the manufacturing test. In this paper, we present a novel flush test procedure to determine if a clock network has any small delay faults. This method does not require any change of the clock network, but it does require a “special test clock signal,” which can be generated on the chip by using only standard cells. Experimental results of transistor-level simulation on benchmark circuits injected with resistive open defects in the layout show that the proposed method is capable of detecting a delay fault as small as 52.8 ps.

Lead poisoning (LP) is less commonly encountered in emergency departments (ED). However, lead exposure still occurs, and new sources of poisoning have emerged. LP often goes unrecognized due to a low index of suspicion and nonspecific symptoms. We present a case of a 48-year-old man who had recurring abdominal pain with anemia that was misdiagnosed. His condition was initially diagnosed as nonspecific abdominal pain and acute porphyria. Acute porphyria-like symptoms with a positive urine porphyrin test result led to the misdiagnosis; testing for heme precursors in urine is the key to the differential diagnosis between LP and acute porphyria. The final definitive diagnosis of lead toxicity was confirmed based on high blood lead levels after detailed medical history taking. The lead poisoning was caused by traditional Chinese herbal pills. The abdominal pain disappeared after a course of chelating treatment. The triad for the diagnosis of lead poisoning should be a history of medicine intake, anemia with basophilic stippling, and recurrent abdominal pain.

ITC celebrates its 50th anniversary in 2019. Over its 50 years of history, the testing of an IC has undergone several stages of paradigm shifts. Today, it is still the most vital path leading to IC's quality, reliability, and robustness. Under this flagship conference, the test community has proliferated in almost every region in the world, following the footsteps of the expansion and diversification of our test industry. It is a constant evolution process, and ITC-Asia was born in 2017, to mark another milestone in this globalization process, with an attempt to integrate more people from both academia and industry, especially those in Asia, into a unified worldwide test community.

This paper discusses how to perform online integrity checking for a clock system spanning all over a heterogeneously integrated IC. A clock system in this work is assumed to consist of two major components - (1) the Delay-Locked Loop (DLL), commonly used for module-to-module clock synchronization, and (2) the clock distribution network (with clock buffers and interconnects). For the DLL part, we incorporate a “phase error monitoring scheme”, which is able to detect abnormal safety hazard, e.g., an instantaneous power glitch. For the clock distribution network, we incorporate a periodic self-test scheme featuring a “special short-pulse driven flush test procedure” to detect any worsening Clock Delay Fault (CDF). The proposed method can help identify a failure threat before it strikes havoc. Post-layout simulation results are presented to demonstrate the effectiveness of the proposed schemes.

Traditionally, it has been a difficult task to characterize the quality of a Clock Delay Fault (CDF). Here, a CDF is referred to a delay fault occurring in the clock network that causes an abnormal delay when a clock signal travels through it and thereby causing large-than-expected clock skews at the clock ports of some flip-flops. In a recent work [12], a modified flush test procedure taking short pulses as the test stimuli at selected clock cycles has been proven effective in characterizing a CDF. In this work, we extend this technique to support online Built-In Self-Test (BIST). We investigate two fault detection strategies, namely, valid-range criterion, and valid-span criterion, and we compare their fault detection abilities in terms of the minimum detectable CDF. With the proposed BIST scheme, the health condition of the clock network in a device operating in the field can be inspected on a regular basis so as to take precautions before the clock network breaks down due to deteriorating fault effects.

The Tunable Delay Line (TDL) is the most important building block in a modern cell-based timing circuit such as Phase-Locked Loop (PLL) or Delay-Locked Loop (DLL). In previously proposed TDLs, one dilemma exists -- they cannot be both power efficient and environmentally adaptive at the same time. In this paper, we present an effective solution for such a dilemma - a novel "ping-pong delay line" architecture. The idea is to use two small cell-based delay lines operated in a synergistic manner in the sense that they exchange the "role of command" dynamically like in a ping-pong game, and thereby jointly reacting to severe environmental changes over a very wide range. This proposed ping-pong delay line has been incorporated in a Delay-Locked Loop (DLL) design, to demonstrate its advantages by post-layout simulation.

In this paper, we present a cell-based wide-frequency-range DLL supporting clock frequencies from 10MHz to 1GHz in 90nm. To support fast locking (during frequency scaling), we present novel architecture with a socalled “fast-locking mode” - in which the control code for the Long-Range Delay Block (LRDB) can be quickly determined in a way that the overall delay across the underlying DLL can be roughly one or multiple clock cycle times of the input clock signal. One can use this LRDB as a common building block and integrate it with any arbitrary narrow-range DLL for DVFS (Dynamic Voltage and Frequency Scaling) applications while achieving fast frequency scaling. The functionality is validated by post-layout simulation using a 90nm CMOS process. With the proposed scheme, the long-range locking time can be reduced significantly from 24% to 98%, respectively, for different input clock frequencies.

Diagnosis of intermittent scan chain failures remains a hard problem. We demonstrate that Artificial Neural Networks (ANNs) can be used to achieve significantly higher accuracy. The key is to take on domain knowledge and use a multi-stage process incorporating ANNs with gradually refined focuses. Experimental results on benchmark circuits show that this method is, on average, 20% more accurate than a state-of-the-art commercial tool for intermittent stuck-at faults, and improves the hit rate from 25.3% to 73.9% for some test-case.

To explore the potential targets and mechanism of Strychni Semen in the nervous system through network pharmacology and molecular docking, in this study, TCMSP, PubChem, and Swiss Target Prediction databases were used to screen the active ingredients and targets of Strychni Semen; related targets of the nervous system were screen out through GeneCards and OMIM databases; the common targets of the two were input into the STRING online analysis platform to construct potential protein interactions (PPI) network. The Cytoscape 3.7.2 software was used to construct a “component-target” network diagram; then the Metascape platform was used to perform GO and KEGG enrichment analysis on its core targets; and the core target was verified by molecular docking with the active ingredient of Strychni semen. In the results, the screening in Strychni Semen with OB ≥ 30% and DL ≥ 0.18% as the threshold values obtained a total of 15 active ingredients and corresponding 384 potential targets; searched for diseases with “neurological” as keywords, 34769 related targets were mapped to potential drug targets, and 61 common targets were obtained; 74 nodes and 173 edges were read in the “component-target” network diagram; enriched in GO and KEGG A total of 11 signal pathways with significant differences were obtained in the analysis; molecular docking showed that the compounds in Strychni Semen have high binding energy to key proteins of the nervous system. In conclusion, the study initially explored the potential mechanism of Strychni Semen’s multi-pathway and multi-target action on the nervous system, providing scientific basis for the clinical application and in-depth research of the decoction piece.

Online monitoring of interconnect delay is important for early detection of reliability hazards, especially in multidie ICs. This article presents a versatile, low-overhead, and nonintrusive monitoring scheme to detect the worst case transition time of interconnects.

Detection of delay faults in 3-D interconnects is crucial for building reliable 3-D ICs. This paper presents a test methodology based on a globalring structure with a variable output thresholding technique to detect delay faults in multipin 3-D interconnects in multidie 3-D ICs. The proposed test architecture with an enhanced clock period measurement circuit detects delay faults in multipin 3-D interconnects with an accuracy of 10 ps.

This paper presents a radar system for extracting human respiratory features. The proposed radar chip comprises three major components: a digital-to-time converter (DTC), a transmitter, and a receiver. The all-digital standard cell-based DTC achieves a timing resolution of 10 ps on a 100-ns time scale, supporting a range-gated sensing process. The transmitter is composed of a digital pulse generator. The receiver comprises a direct-sampling passive frontend for achieving high linearity, an integrator for enhancing the signal-to-noise ratio, and a successive approximation register analog-to-digital converter for signal quantization. A fully integrated CMOS impulse radar chip was fabricated using 65-nm CMOS technology, and the total power consumption is 21 mW. In the backend, a real-time digital signal-processing platform captures human respiratory waveforms via the radar chip and processes the waveforms by applying a human respiratory feature extraction algorithm. Furthermore, a clinical trial was conducted for establishing a new diagnosis workflow for identifying respiratory diseases by the proposed wireless sensor system. The proposed system was validated by applying an adaptive network-based fuzzy inference system and support vector machine algorithm to the clinical trial results. These algorithms confirmed the effectiveness of the proposed system in diagnosing respiratory diseases.

In this work, we present a long-range delay block for a wide range DLL supporting clock rates from 10MHz to 1GHz. The main contribution is a fast-locking scheme that quickly decides the control code of the delay block using a folded scheme. Post-layout simulation using a 90nm CMOS process has demonstrated that the locking time can he slashed dramatically.

In this work, we present the first cell-based Fractional-N Phase-Locked Loop (PLL) compiler, according to the best of our knowledge. Unlike its previous integer-N PLL compiler, a target clock frequency can be generated precisely with an almost arbitrary input reference clock frequency. For example, 1 GHz output clock can be generated from a given 17.33MHz reference clock. With a search engine, such a compiler can find a small-area as well as low-power PLL configuration within minutes. We also have verified its ability for two process nodes (i.e., 90nm and 180nm) by transistor-level simulation on seven test-case PLL macros generated by this compiler. Experimental results show that they can indeed function correctly under extreme PVT conditions.

Die-to-die interconnects linking multiple functional dies in a modern 3-D or 2.5-D IC by micro-bumps could experience resistance increase after certain time of field operation due to parametric defects or aging. To cope with this reliability threat, we present an “on-line transition-time binning method” that aims to continuously detect excessive transition time occurring at a target die-to-die interconnect. Our method attaches a monitor to the termination end of each target interconnect. Any transition (rising or falling) is converted into a pulse-width first, which is then further compared to a dynamically tunable threshold for a binary pass/fail judgment. By multiple runs of transition-time monitoring while sweeping the threshold incrementally, the “transition-time bin” of each target interconnect can be derived and thereby a timing failure threat can be detected by a monitor center before it actually strikes.

A faulty interposer in a 2.5-D integrated circuit often results in a hefty loss as the potentially expensive known-good-dies bonded on the interposer will have to be discarded as well. To avoid such a last-minute loss during a multichip integration process, built-in self-repair (BISR) is highly valuable. Even though there have been many BISR schemes in the literature, the proposed method offers a number of distinct features. First, it can target not only catastrophic faults, but also timing faults. Second, it can be applied to general multi-pin interconnects and it can be applied to repair an interposer with multiple faulty interconnects. Third, it can perform the test-and-then-repair flow on-the-fly, and thereby eliminating the overhead of extra repair storage incurred in previous methods.

Embedded multicore systems are playing increasingly important roles in the design of consumer electronics. The objective of such systems is to optimize both performance and power characteristics of mobile devices. However, currently there are no power metrics supporting popular application design platforms (such as SID) that application developers use to develop their applications. This hinders the ability of application developers to optimize power consumption. In this article we present the design and experiments of a SID-based power-aware simulation framework for embedded multicore systems. The proposed power estimation flow includes two phases: IP-level power modeling and power-aware system simulation. The first phase employs PowerMixer IP to construct the power model for the processor IP and other major IPs, while the second phase involves a power abstract interpretation method for summarizing the simulation trace, then, with a CPE module, estimating the power consumption based on the summarized trace information and the input of IP power models. In addition, a Manager component is devised to map each digital signal processor (DSP) component to a host thread and maintain the access to shared resources. The aim is to maintain the simulation performance as the number of simulated DSP components increases. A power-profiling API is also supported that developers of embedded software can use to tune the granularity of power-profiling for a specific code section of the target application. We demonstrate via case studies and experiments how application developers can use our SID-based power simulator for optimizing the power consumption of their applications. We characterize the power consumption of DSP applications with the DSPstone benchmark and discuss how compiler optimization levels with SIMD intrinsics influence the performance and power consumption. A histogram application and an augmented-reality application based on human-face-based RMS (recognition, mining, and synthesis) application are deployed as running examples on multicore systems to demonstrate how our power simulator can be used by developers in the optimization process to illustrate different views of power dissipations of applications.

For a multi-die IC, the chip-level clock synchronization problem that aims to establish a global clock signal across multiple functional dies is harder to achieve than its single-die counterpart. In this work, we investigate a process resilient solution for this problem by incorporating Delay-Locked Loops (DLLs). The basic idea is to insert a DLL (which can be generated by a DLL compiler) in each functional die so that the clock latency (from a clock source to the clock ports of a number of FFs) in different dies can be dynamically tuned and equalized. This method has a benefit that the clock network of each die can be designed independently, while the clock skew of the entire chip can still be minimized at run-time, in response to its operating environment. In a preliminary study, experimental results on a pseudo 4-die design demonstrates how the clock skew as high as 233ps initially can be reduced to 34ps after the application of the proposed method.

Reliability of an IC, concerning if an IC can function reliably over its designated lifetime in the field, has become more and more important in today's safety-critical applications. It is known that reliability can be affected by PVT effects, (Process, Voltage, Temperature). These effects not only depend on the physical locations where an IC is operated, but also vary over time. In this work, we present a cloud-based PVT monitoring system for the Internet of Things (IoT) devices, by taking advantage of its inherent internet connectivity. By doing so, one can know of the PVT status of any IoT device remotely and continually at any time and any place. With the obtained information, a potential PVT-induced failure can be alarmed in advance before it actually strikes, and thereby pre-cautious actions (such as adaptive measures, online repair, or even manual replacement) can be taken in advance to avoid unnecessary system down time.

We conducted a retrospective study to compare clinical and laboratory findings between 1) severe influenza A and mild influenza A and 2) pandemic 2009 H1N1 (pdm09 A/H1) and seasonal H3N2 (A/H3) from 2009 to 2010. A total of 526 (mean age, 13.6 years; 447 pdm09 A/H1, 79 seasonal A/H3) patients were included, 41 (7.8%) with severe influenza (mean age, 28.1 years; 26 pdm09 A/H1, 15 seasonal A/H3). Influenza-associated complications were pneumonia (75.6%), meningoencephalitis (14.6%), acute kidney injury (14.6%), and acute respiratory distress syndrome (12.2%). Patients with seasonal A/H3 were significantly less likely to experience sore throat (P < 0.001), malaise (P < 0.001), and muscle pain (P < 0.001); they were significantly more likely to have hypertension (P < 0.001), diabetes mellitus (P = 0.001), and chronic obstructive pulmonary disease (P < 0.001), delayed hospital presentation (P = 0.001), delayed oseltamivir treatment (P < 0.001), and higher in-hospital mortality (P = 0.02) than patients with pdm09 A/H1. Further comparison between severe pdm09 A/H1 and severe seasonal A/H3 revealed that severe seasonal A/H3 patients (median age, 71 years) were significantly older than patients with severe pdm09 A/H1 (median age, 7 years) (P < 0.001). Comparison between severe influenza and mild influenza, regardless of influenza A subtypes, by multivariate analysis, found that tachypnea (odds ratio [OR] = 44.3, 95% confidence interval [CI] = 15.7-124.6) and delayed oseltamivir therapy ≧ 48 hours after illness onset (OR = 3.7, 95% CI = 1.3-10.5) were independent risk factors for severe influenza. The findings of this study will improve the understanding of the clinical differences between pdm09 A/H1 and seasonal A/H3, and of influenza-associated complications and predictors for severe outcomes that can help to direct clinicians toward the most effective management of influenza patients to reduce the preventable mortality and morbidity.

This paper proposes a resilient Time-to-Digital Converter (TDC) that lends itself to cell-based design automation. We adopt a shrinking-based architecture with a number of distinctive techniques. First of all, a specialized on-chip re-calibration scheme is developed so that the real-time transfer function of the TDC in silicon (which maps an input pulse-width to its corresponding output code) can be derived on the chip and thereby the absolute value (instead of just a relative code) of an input pulse-width under measurement can be reported. Secondly, the sampling errors stemming from the jitters of training clocks used in the calibration scheme are mitigated by the principle of multi sampling. Thirdly, a flexible coarse-shrinking block is adopted and an automatic adjustment scheme is employed so that the coarse-shrinking block can adjust itself when operated under different input pulse-width ranges.

During a multi-die integration process, a number of known good dies are stitched together by die-to-die interconnects composed of TSVs (Through Silicon Vias) and/or die-to-die interconnecting wires. These die-to-die interconnects are not only used for signal transmission, but also for clock and power distribution. In this talk, we review some potential test methods that can be used for these two types of logistic die-to-die interconnects. Different from a simple pass or fail test, these methods often require a sophisticated characterization process that quantifies the effect of a parametric defect or the amount of variation. They can help diagnose the culprit of a failed IC to determine if it is due to the clock or power distribution network, and also suggest ways to recover from the failure when it is only parametric or variational.