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Time Series Analysis (TSA) is a critical workload for consumer-facing devices. Accelerating TSA is vital for many domains as it enables the extraction of valuable information and predict future events. The state-of-the-art algorithm in TSA is the subsequence Dynamic Time Warping (sDTW) algorithm. However, sDTW's computation complexity increases quadratically with the time series' length, resulting in two performance implications. First, the amount of data parallelism available is significantly higher than the small number of processing units enabled by commodity systems (e.g., CPUs). Second, sDTW is bottlenecked by memory because it 1) has low arithmetic intensity and 2) incurs a large memory footprint. To tackle these two challenges, we leverage Processing-using-Memory (PuM) by performing in-situ computation where data resides, using the memory cells. PuM provides a promising solution to alleviate data movement bottlenecks and exposes immense parallelism. In this work, we present MATSA, the first MRAM-based Accelerator for Time Series Analysis. The key idea is to exploit magneto-resistive memory crossbars to enable energy-efficient and fast time series computation in memory. MATSA provides the following key benefits: 1) it leverages high levels of parallelism in the memory substrate by exploiting column-wise arithmetic operations, and 2) it significantly reduces the data movement costs performing computation using the memory cells. We evaluate three versions of MATSA to match the requirements of different environments (e.g., embedded, desktop, or HPC computing) based on MRAM technology trends. We perform a design space exploration and demonstrate that our HPC version of MATSA can improve performance by 7.35x/6.15x/6.31x and energy efficiency by 11.29x/4.21x/2.65x over server CPU, GPU and PNM architectures, respectively., arXiv

Time Series Analysis (TSA) is a critical workload for consumer-facing devices. Accelerating TSA is vital for many domains as it enables the extraction of valuable information and predict future events. The state-of-the-art algorithm in TSA is the subsequence Dynamic Time Warping (sDTW) algorithm. However, sDTW's computation complexity increases quadratically with the time series' length, resulting in two performance implications. First, the amount of data parallelism available is significantly higher than the small number of processing units enabled by commodity systems (e.g., CPUs). Second, sDTW is bottlenecked by memory because it 1) has low arithmetic intensity and 2) incurs a large memory footprint. To tackle these two challenges, we leverage Processing-using-Memory (PuM) by performing in-situ computation where data resides, using the memory cells. PuM provides a promising solution to alleviate data movement bottlenecks and exposes immense parallelism. In this work, we present MATSA, the first MRAM-based Accelerator for Time Series Analysis. The key idea is to exploit magneto-resistive memory crossbars to enable energy-efficient and fast time series computation in memory. MATSA provides the following key benefits: 1) it leverages high levels of parallelism in the memory substrate by exploiting column-wise arithmetic operations, and 2) it significantly reduces the data movement costs performing computation using the memory cells. We evaluate three versions of MATSA to match the requirements of different environments (e.g., embedded, desktop, or HPC computing) based on MRAM technology trends. We perform a design space exploration and demonstrate that our HPC version of MATSA can improve performance by 7.35x/6.15x/6.31x and energy efficiency by 11.29x/4.21x/2.65x over server CPU, GPU and PNM architectures, respectively.

Trabajo de Investigación Este trabajo se enfoca en el uso de asfalto reciclado (RAP) y 2 porcentajes de adición de Cal del 3% y 6% más Emulsión asfáltica en frio, en las que se fabricaron probetas por cada contenido de Cal y las mismas se sometieron a diferentes tipos de ensayos los cuales a partir de los resultados nos permitieron evaluar el comportamiento físico mecánico respecto a una mezcla de control con 0% de adición de Cal. Especialización Especialista en Ingeniería de Pavimentos INTRODUCCIÓN 1. GENERALIDADES 2. OBJETIVOS 3. MARCOS DE REFERENCIA 4. METODOLOGIA 5. CONCLUSIONES Y RECOMENDACIONES BIBLIOGRAFÍA ANEXOS

Trabajo de investigación El presente proyecto de grado tiene como fin realizar la valoración del grado de madurez en la gestión de proyectos de la empresa GUSTAVO PERRY ARQUITECTOS S.A.S, identificando las practicas y estándares de la gerencia de proyectos aplicados a proyectos de diseño, se conoció el grado de madures por grupos de procesos y por ultimo se propusieron estrategias y herramientas a mediano y corto plazo para el mejoramiento del grado de madurez. Especialización Especialista en Gerencia de Obras Civiles INTRODUCCIÓN 1. GENERALIDADES 2. MARCOS DE REFERENCIA 3. METODOLOGÍA 4. RESULTADOS 5. ANÁLISIS DE RESULTADOS E IMPACTOS 6. PROPUESTA DE MEJORA DE LA CULTURA DE PROYECTOS EN LA EMPRESA GUSTAVO PERRY ARQUITECTOS S.A.S 7. CONCLUSIONES BIBLIOGRAFÍA ANEXOS

espanolEl tema de la familia involucrada en el contexto educativo ha sido una constante discusion abordada desde diferentes areas del saber, llegando a coincidir en la necesidad de involucrarlos en los procesos de ensenanza, porque asi se consolidan en los estudiantes competencias e intereses por la educacion. A partir de esto se platea como proposito de esta investigacion, fortalecer los procesos educativos a traves de las Tecnologias de la informacion y la comunicacion (TIC), involucrando en el proceso de ensenanza aprendizaje a padres de familia y/o cuidadores. Se tomo como unidad de analisis a 20 padres de familias y 9 cuidadores de los estudiantes del quinto grado A (5°a) y quinto B (5°b), de la Institucion Educativa Departamental Maria Inmaculada del Municipio de Pivijay Magdalena, la metodologia empleada se oriento desde el enfoque cualitativo, con alcance es descriptivo. Dentro de los hallazgos del estudio se encontro que la mayoria de los padres y/o cuidadores afirman emplear el computador y el internet para ayudar a los estudiantes a realizar sus tareas; que al trabajar de la mano padre y estudiantes, mediados por TIC se fortalecen los procesos pedagogicos y los lazos afectivos entre estos. EnglishThe theme of the family involved in the educational context has been a constant discussion addressed from different areas of knowledge, coming to agree that by involving them in the teaching processes, students' competences and interests for education are consolidated. Therefore, the present research is aimed at strengthening educational processes through Information and Communication Technologies (TIC) involving parents and / or caregivers in the teaching-learning process. The unit of analysis was constituted by the students of 5th a and b of the Departmental Educational Institution Maria Inmaculada of the Municipality of Pivijay Magdalena. The methodology used was oriented from the Qualitative Approach, with scope is descriptive. Among the findings of the study it was found that most parents and / or caregivers claim to use the computer and the internet to help students perform their tasks; that by working hand in hand with parents and students, mediated by ICT, the pedagogical processes and the affective bonds between them are strengthened.

106 páginas : ilustraciones, gráficos. In recent decades our world view has been characterized by crisis in economic, social and environmental terms; a situation which requires the administrative structures to achieve their goals or objectives in this adverse environment and implement strategies that allow them to remain competitive and at the same time play a fundamental role in the development of the country. Chapter one begins with the approach of the problem, this in turn will recorded history by addressing the research questions, defining the general objective and specific to establish the limits and scope of the investigation and end up supporting the justification of this research. In chapter two, presents the framework that supports the theoretical characterization of the ethical values such as confidence, responsibility, respect and honesty, teamwork and effectiveness on the projects, which are the three variables of the present study research. In chapter three, discussed the main actors of the public management in the energy mining sector and the relationship they have with corruption, taking into account that this is the sector that focuses the present project, its history, the evolution of power and the projects that have been implemented. En las ultimas décadas nuestro panorama mundial se ha caracterizado par crisis en términos económicos, sociales y ambientales; situación que obliga a las estructuras administrativas a lograr sus metas u objetivos en este ambiente adverso e implementar estrategias que le permitan mantenerse competitivas y jugar a su vez un papel fundamental en el desarrollo del país. El capítulo uno comienza con el planteamiento del problema, este a su vez va registrando los antecedentes abordando las preguntas de investigación, definiendo el objetivo general y específicos para establecer las límites y alcances de la investigación y terminar soportando la justificación de esta investigación. En el capítulo dos, se presenta el marco que soporta la caracterización teórica de los valores éticos como confianza, responsabilidad, respeto y honestidad, el trabajo en equipo y la efectividad en los proyectos, que son las tres variables objeto de estudio de la presente investigación. En el capítulo tres, se analizan los principales actores de la gestión pública en el sector minero energético y la relación que estos, tienen con la corrupción, teniendo en cuenta que este es el sector al que está enfocado el presente proyecto, su historia, la evolución de la energía y los proyectos que se han ejecutado. Maestría Magíster en Gestión y Evaluación de Proyectos de Inversión

Visita Técnica Internacional El alcance del proyecto se desarrolla con base en la visita internacional a la empresa CEMEX ubicada en México, la cual se caracteriza por la fabricación de concretos y que también cuenta con presencia en Colombia, lo que permite llevar a cabo una identificación de aspectos comunes y diferenciales a partir de la recopilación de la información acerca de los controles de calidad en concretos. Con ello se logró:  Conocer los procesos de ensayo de caracterización para el control de calidad del concreto de una de las mejores plantas de Cemex a nivel mundial.  Realizar un análisis comparativo con los procesos colombianos.  Determinar cuáles procesos pueden ser aplicados en la industria colombiana. Igualmente, se realizó un recorrido por la normatividad y normas técnicas aplicables en Colombia; donde se definen los parámetros o estándares de calidad determinados por los ensayos que estipulan la resistencia y durabilidad de los concretos, producto utilizado en la construcción y ejecución de proyectos de ingeniería civil. Con ello se realizó un análisis comparativo entre la normatividad colombiana y la mexicana. Pregrado Ingeniero Civil INTRODUCCIÓN 1. GENERALIDADES 2. PLANTEAMIENTO DEL PROBLEMA 3. OBJETIVOS 4. JUSTIFICACIÓN 5. DELIMITACIÓN 6. MARCO REFRENCIAL 7. METODOLOGÍA 8. RESULTADOS VISITA TÉCNICA INTERNACIONAL 9. RESULTADOS VISITA TÉCNICA NACIONAL 10. ANÁLISIS DE RESULTADOS 11. CONCLUSIONES 12. RECOMENDACIONES 13. BIBLIOGRAFÍA 14. ANEXOS

The heterogeneous Accelerated Processing Units (APUs) integrate a multi-core CPU and a GPU within the same chip. Modern APUs provide the programmer with platform atomics, used to communicate the CPU cores with the GPU using simple atomic datatypes. However, ensuring consistency for complex data types is a task delegated to programmers, who have to implement a mutual exclusion mechanism. Transactional Memory (TM) is an optimistic approach to implement mutual exclusion. With TM, shared data can be accessed by multiple computing threads speculatively, but changes are only visible if a transaction ends with no conflict with others in its memory accesses. TM has been studied and implemented in software and hardware for both CPU and GPU platforms, but an integrated solution has not been provided for APU processors. In this paper we present APUTM, a software TM designed to work on heterogeneous APU processors. The design of APUTM focuses on minimizing the access to shared metadata in order to reduce the communication overhead via expensive platform atomics. The main objective of APUTM is to help us understand the tradeoffs of implementing a sofware TM on an heterogeneous CPU-GPU platform and to identify the key aspects to be considered in each device. In our experiments, we compare the adaptability of APUTM to execute in one of the devices (CPU or GPU) or in both of them simultaneously. These experiments show that APUTM is able to outperform sequential execution of the applications. This work has been supported by projects TIN2013-42253-P and TIN2016-80920-R, from the Spanish Government, P11-TIC8144 and P12- TIC1470, from Junta de Andalucía, and Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech.

In the multi-core CPU world, transactional memory (TM)has emerged as an alternative to lock-based programming for thread synchronization. Recent research proposes the use of TM in GPU architectures, where a high number of computing threads, organized in SIMT fashion, requires an effective synchronization method. In contrast to CPUs, GPUs offer two memory spaces: global memory and local memory. The local memory space serves as a shared scratch-pad for a subset of the computing threads, and it is used by programmers to speed-up their applications thanks to its low latency. Prior work from the authors proposed a lightweight hardware TM (HTM) support based in the local memory, modifying the SIMT execution model and adding a conflict detection mechanism. An efficient implementation of these features is key in order to provide an effective synchronization mechanism at the local memory level. After a quick description of the main features of our HTM design for GPU local memory, in this work we gather together a number of proposals designed with the aim of improving those mechanisms with high impact on performance. Firstly, the SIMT execution model is modified to increase the parallelism of the application when transactions must be serialized in order to make forward progress. Secondly, the conflict detection mechanism is optimized depending on application characteristics, such us the read/write sets, the probability of conflict between transactions and the existence of read-only transactions. As these features can be present in hardware simultaneously, it is a task of the compiler and runtime to determine which ones are more important for a given application. This work includes a discussion on the analysis to be done in order to choose the best configuration solution. Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech.

Hardware vendors make an important effort creating low-power CPUs that keep battery duration and durability above acceptable levels. In order to achieve this goal and provide good performance-energy for a wide variety of applications, ARM designed the big.LITTLE architecture. This heterogeneous multi-core architecture features two different types of cores: big cores oriented to performance and little cores, slower and aimed to save energy consumption. As all the cores have access to the same memory, multi-threaded applications must resort to some mutual exclusion mechanism to coordinate the access to shared data by the concurrent threads. Transactional Memory (TM) represents an optimistic approach for shared-memory synchronization. To take full advantage of the features offered by software TM, but also benefit from the characteristics of the heterogeneous big.LITTLE architectures, our focus is to propose TM solutions that take into account the power/performance requirements of the application and what it is offered by the architecture. In order to understand the current state-of-the-art and obtain useful information for future power-aware software TM solutions, we have performed an analysis of a popular TM library running on top of an ARM big.LITTLE processor. Experiments show, in general, better scalability for the LITTLE cores for most of the applications except for one, which requires the computing performance that the big cores offer. Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech.

Los aceleradores gráficos (GPUs) se han convertido en procesadores de prop ́osito general muy populares para el cómputo de aplicaciones que presen- tan un gran paralelismo de datos. Su modelo de ejecución SIMT (Single Instruction - Multiple Thread) y su jerarquía de memoria son piezas clave en la alta eficiencia de estas arquitecturas, que permiten el manejo de cientos o miles de hilos de ejecución. La jerarquía de memoria está dividida en dos espacios direccionables: Una memoria local, pequeña, rápida y visible por un subconjunto de los hilos en ejecución; y una memoria global, mayor, más lenta y visible por todos los hilos. Sin embargo, el modelo de programación SIMT no es eficiente cuando hay que sincronizar este desbordante número de hilos para garantizar exclusión mútua en una sección crítica. Utilizar atómicos para implementar cerrojos es problemático e ineficiente en este tipo de modelo de programación. La memoria transaccional (TM) ha sido propuesta como una alternativa más fiable y eficiente que los cerrojos para esta sincronización. Con TM, se permite el acceso especulativo a la sección crítica, registrando los accesos a memoria, deshaciendo los cambios de aquellos hilos que han tenido un conflicto y reiniciando su ejecución. En este trabajo presentamos una solución TM hardware que sincroniza aquellos hilos de ejecución que comparten la memoria local. En las pruebas realizadas, el uso de TM permite conseguir aceleraciones superiores a las soluciones basadas en cerrojos de grano grueso, así como igualar a aquellas basadas en cerrojos de grano fino, pero con un menor esfuerzo de programación. Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech.

Graphics Processing Units (GPUs) are popular hardware accelerators for data-parallel applications, enabling the execution of thousands of threads in a Single Instruction - Multiple Thread (SIMT) fashion. However, the SIMT execution model is not efficient when code includes critical sections to protect the access to data shared by the running threads. In addition, GPUs offer two shared spaces to the threads, local memory and global memory. Typical solutions to thread synchronization include the use of atomics to implement locks, the serialization of the execution of the critical section, or delegating the execution of the critical section to the host CPU, leading to suboptimal performance. In the multi-core CPU world, transactional memory (TM) was proposed as an alternative to locks to coordinate concurrent threads. Some solutions for GPUs started to appear in the literature. In contrast to these earlier proposals, our approach is to design hardware support for TM in two levels. The first level is a fast and lightweight solution for coordinating threads that share the local memory, while the second level coordinates threads through the global memory. In this paper we present GPU-LocalTM as a hardware TM (HTM) support for the first level. GPU-LocalTM offers simple conflict detection and version management mechanisms that minimize the hardware resources required for its implementation. For the workloads studied, GPU-LocalTM provides between 1.25-80X speedup over serialized critical sections, while the overhead introduced by transaction management is lower than 20%. Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech.

The compute nodes in contemporary HPC systems contain one or more multicore processors. As a result, these nodes constitute a shared-memory multiprocessor, often combining CMP and SMT concurrency technologies. This configuration introduces different levels of sharing in the cache hierarchy, resulting in non-uniform data sharing overheads. In this paper we analyze the data-sharing patterns that exhibit a real multithreaded application when executing on a multicore system, with emphasis in the use of the shared last level cache (LLC) for the concurrent threads. As a consequence of this study, we explore the loop mapping problem in such systems with the aim of optimizing the shared use of the the LLC by all parallel threads. We propose a three-phase loop mapping strategy that deals with workload imbalances, minimizes cache sharing interferences, and maximizes intra-core and inter-core data reuse in the cache hierarchy. Preliminary results show some benefits of our approach. However, this is a work in progress and much more research is being done.

Fuente TESIUNAM