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Case Study 3: Palazzina della Viola, Bologna, Italy

The longevity of wireless sensor network (WSN) deployments is often crucial for real-time monitoring applications. Minimizing energy consumption by utilizing intelligent information processing is one of the main ways to prolong the lifetime of a network deployment. Data streams from the sensors need to be processed within the resource constraints of the sensing platforms to reduce the energy consumption associated with packet transmission. In this paper we carried out both simulation and real-world implementation of light-weight adaptive models to achieve a prolonged WSN lifetime. Specifically, we propose a Naive model that incurs virtually no cost with low memory footprint to realize this goal. Our results show that, despite its minimal complexity, the Naive model is robust when compared with other well-known algorithms used for prediction in WSNs. We show that our approach achieves up to 96% communication reduction, within 0.2 degrees error bound with no significant loss in accuracy and it is comparable in performance to the more complex algorithms like Exponential Smoothing (ETS).

Data reduction strategy is one of the schemes employed to extend network lifetime. In this paper we present an implementation of a light-weight forecasting algorithm for sensed data which saves packet transmission in the network. The proposed Naive algorithm achieves high energy savings with a limited computational overhead on a node. Simulation results from realistic Building monitoring application of WSN are compared with well-known prediction algorithms such as ARIMA, LMS and WMA models. We implemented a real-world deployment using 32bit mote-class device. Overall, up to 96% transmission reduction is achieved using our Naive method, while still able to maintain a considerable level of accuracy at 0.5 degrees C error bound and it is comparable in performance to the more complex models such as ARIMA, LMS and WMA.

Data reduction strategy is one of the schemesemployed to extend network lifetime. In this paper we present an implementation of a light-weight forecasting algorithm for sensed data which saves packet transmission in the network. The proposed Naive algorithm achieves high energy savings with a limited computational overhead on a node. Simulation results from realistic Building monitoring application of WSN are compared with well-known prediction algorithms such as ARIMA, LMS and WMA models. We implemented a real-world deployment using 32bit mote-class device. Overall, up to 96%transmission reduction is achieved using our Naive method, while still able to maintain a considerable level of accuracy at 0.5 degrees error bound and it is comparable in performance to the more complex models such as ARIMA, LMS and WMA.

In this paper, we propose SWIFTNET: a fast-reactive data acquisition scheme. SWIFTNET is built on the synergies between compressive sensing and prediction algorithms and limits the energy consumption in environmental monitoring and surveillance networks. We show how this approach dramatically reduces the amount of communication required to monitor the sensor readings in a deployment. We use a wildfire monitoring application that requires high reactiveness with continuous data updates of the monitoring process. Experimental results show that over 50% communication reduction is achieved without loss in accuracy over the common prediction approach. In addition, reactiveness is guaranteed by adjusting the sampling rate from 5 minutes up to 15 seconds.

The most up-to-date research interests in energy efficiency in historical buildings highlight the necessity to integrate the structural and energetic viewpoints, starting from a diagnostic phase, prior to designing the interventions. A wireless sensor network was installed at Palazzina della Viola, Bologna, Italy, and equipped with sensors for monitoring indoor environmental parameters such as air temperature, relative humidity, light, semiconductor metal oxide (MOX) Gas sensor interfaces; in addition 3-axis accelerometers for monitoring structural vibrations. The network is made of about 40 nodes, distributed on the different building levels and acquiring data from the whole building. The sensor nodes are placed in static position, except for 6 nodes concentrated in the large hall and front loggia, both with frescoes, on the 1st floor. Those 6 nodes may be used as mobile stations in order to carry out specific measurement campaigns or dynamic surveys. They may be employed to corroborate data recorded by different or alternative testing techniques. Presently, of particular interest seems to be the verification of aspects such as: a) light distribution in the different rooms for example pre- and post- interventions or with natural/artificial light; b) vibration levels before, during and after structural/energetic refurbishment; c) air flow dynamics between rooms of different volumes, heights, sun exposure. This work presents the methodology of using dynamic wireless sensor monitoring in combination or as an alternative to traditional or innovative indoor climate survey and structural testing.

Air quality monitoring in indoor environments is of great significance for comfort and health, especially nowadays that people spend more than 80% of the day indoor. We propose a flexible wireless system able to detect polluted air and dangerous situations in a complex and large environment. It is important for ambient intelligent systems to be unobtrusive and to optimize the power consumption of the platforms in order to be able to live on batteries for several years. We present a system with aggressive energy management that involves three levels: sensor level, node level and network level. The sensor board we designed is a wireless sensor network (WSN) node, with very low sleep current consumption (only 8 A). It contains two modalities — a gas sensor and a Pyroelectric InfraRed (PIR) sensor. The network is multimodal: it uses information from the PIR sensor and neighbor nodes to detect the presence of people and to modulate the duty cycle of the node and the Metal Oxide Semiconductor (MOX) gas sensor. In this way we reduce the nodes’ activity and energy requirements, providing a reliable service at the same time. We simulate the benefits of the context-aware adaptive duty-cycling of the gas sensor activity and we demonstrate a significant lifetime extension compared to the continuously driven gas sensor (several years vs. several days).

The SMILING project is aimed at providing a technological solution to motor problems, particularly related to gait and balance such as the risk of falling, occurring in the elderly population. The contribution of the present paper is to provide an insight on the SMILING system prototype with a particular focus on the User Control Unit, that is a portable, wireless device designed to assist the user during training and to control the interaction with the different parts of the system. Furthermore, integration aspects are introduced and preliminary tests of the system with young healthy subjects are described.

The digital electronic market development is founded on the continuous reduction of the transistors size, to reduce area, power, cost and increase the computational performance of integrated circuits. This trend, known as technology scaling, is approaching the nanometer size. The lithographic process in the manufacturing stage is increasing its uncertainty with the scaling down of the transistors size, resulting in a larger parameter variation in future technology generations. Furthermore, the exponential relationship between the leakage current and the threshold voltage, is limiting the threshold and supply voltages scaling, increasing the power density and creating local thermal issues, such as hot spots, thermal runaway and thermal cycles. In addiction, the introduction of new materials and the smaller devices dimension are reducing transistors robustness, that combined with high temperature and frequently thermal cycles, are speeding up wear out processes. Those effects are no longer addressable only at the process level. Consequently the deep sub-micron devices will require solutions which will imply several design levels, as system and logic, and new approaches called Design For Manufacturability (DFM) and Design For Reliability. The purpose of the above approaches is to bring in the early design stages the awareness of the device reliability and manufacturability, in order to introduce logic and system able to cope with the yield and reliability loss. The ITRS roadmap suggests the following research steps to integrate the design for manufacturability and reliability in the standard CAD automated design flow: i) The implementation of new analysis algorithms able to predict the system thermal behavior with the impact to the power and speed performances. ii) High level wear out models able to predict the mean time to failure of the system (MTTF). iii) Statistical performance analysis able to predict the impact of the process variation, both random and systematic. The new analysis tools have to be developed beside new logic and system strategies to cope with the future challenges, as for instance: i) Thermal management strategy that increase the reliability and life time of the devices acting to some tunable parameter,such as supply voltage or body bias. ii) Error detection logic able to interact with compensation techniques as Adaptive Supply Voltage ASV, Adaptive Body Bias ABB and error recovering, in order to increase yield and reliability. iii) architectures that are fundamentally resistant to variability, including locally asynchronous designs, redundancy, and error correcting signal encodings (ECC). The literature already features works addressing the prediction of the MTTF, papers focusing on thermal management in the general purpose chip, and publications on statistical performance analysis. In my Phd research activity, I investigated the need for thermal management in future embedded low-power Network On Chip (NoC) devices.I developed a thermal analysis library, that has been integrated in a NoC cycle accurate simulator and in a FPGA based NoC simulator. The results have shown that an accurate layout distribution can avoid the onset of hot-spot in a NoC chip. Furthermore the application of thermal management can reduce temperature and number of thermal cycles, increasing the systemreliability. Therefore the thesis advocates the need to integrate a thermal analysis in the first design stages for embedded NoC design. Later on, I focused my research in the development of statistical process variation analysis tool that is able to address both random and systematic variations. The tool was used to analyze the impact of self-timed asynchronous logic stages in an embedded microprocessor. As results we confirmed the capability of self-timed logic to increase the manufacturability and reliability. Furthermore we used the tool to investigate the suitability of low-swing techniques in the NoC system communication under process variations. In this case We discovered the superior robustness to systematic process variation of low-swing links, which shows a good response to compensation technique as ASV and ABB. Hence low-swing is a good alternative to the standard CMOS communication for power, speed, reliability and manufacturability. In summary my work proves the advantage of integrating a statistical process variation analysis tool in the first stages of the design flow.

With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor System-On-Chip (MPSoC) architectures have become widespread. These new systems are complex to design as they must execute multiple complex applications (e.g. video processing, 3D games), while meeting additional design constraints (e.g. energy consumption or time-to-market). Moreover, the rise of temperature in the die for MPSoC components can seriously affect their final performance and reliability. Therefore, mechanisms to efficiently evaluate complete HW/SW MPSoC designs in terms of energy consumption, temperature, performance and other key metrics are needed. In this paper, we present a new HW/SW FPGA-based emulation framework that allows designers to rapidly extract a number of critical statistics from processing cores, memories and interconnection systems being emulated on a FPGA. This information is then used to interact in real-time with a SW thermal model running on a host computer via an Ethernet port. The results show speed-ups of three orders of magnitude compared to cycle-accurate MPSoC simulators, which enable a very fast exploration of a large range of MPSoC design alternatives at the cycle-accurate level. Finally, our HW/SW framework allows designers to test run-time thermal management strategies with real-life inputs without any loss in the performance of the emulated system.

New tendencies in the consumer electronics market present Multi-Processor Systems-On-Chip (MPSoCs) as a promising solution for meeting the processing demands of upcoming generations of user applications. MPSoCs are complex to design, as they must execute multiple applications (real-time video processing, 3D games), while meeting additional design constraints (energy consumption, time-to-market). When an integrated system is built for a certain MPSoC, the definition of an appropriate floorplan is a very complex task for system integration designers. In fact, deciding a suitable placement of each block in the MPSoC architecture requires taking into account multiple constraints (e.g., power, energy, performance, etc) with values that are specific for each design. Recently, due to the increasing temperature in MPSoCs, thermal behavior has become another key factor to define the placement of each block of the design. In this context, we show how designers will benefit from applying our FPGA-based Emulation Framework to the MPSoC design cycle. Starting with a set of constrains (performance, latency...) and the HW elements of the system, with the help of our exploration tool, the thermal behaviour of different floorplan alternatives can be profiled at an early stage of the development cycle. It will also guide the designer in selecting the right packaging solution for the final chip, minimizing the cost without compromising the chip reliability. Our platform enables thermal monitorization of the final (real) applications over the different architectures, at speeds very close to real time, as opposed to SW simulators.

New tendencies envisage Multi-Processor Systems-On-Chip (MPSoCs) as a promising solution for the consumer electronics market. MPSoCs are complex to design, as they must execute multiple applications (games, video), while meeting additional design constraints (energy consumption, time-to-market). Moreover, the rise of temperature in the die for MPSoCs can seriously affect their final performance and reliability. In this paper, we present a new hardware-software emulation framework that allows designers a complete exploration of the thermal behavior of final MPSoC designs early in the design flow. The proposed framework uses FPGA emulation as the key element to model the hardware components of the considered MPSoC platform at multi-megahertz speeds. It automatically extracts detailed system statistics that are used as input to our software thermal library running in a host computer. This library calculates at run-time the temperature of on-chip components, based on the collected statistics from the emulated system and the final floorplan of the MPSoC. This enables fast testing of various thermal management techniques. Our results show speed-ups of three orders of magnitude compared to cycle-accurate MPSoC simulators