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This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University. On 6th July 2005 the London Olympic bidding committee won the right to host the 2012 Olympic Games. Some seven years later London’s Olympic venues were built on time, Team GB accumulated an unprecedented medal haul and no significant security incidents occurred. These outcomes facilitated an understandable positive evaluation of the 2012 Games. It would be churlish not to be positive; Olympic venues experienced during Games are breathtaking. World records and Olympic contests are exciting. Olympic narratives that bond competitor and audience alike are inclusive and unifying. However, the prevalent belief that Olympic hosting provides unambiguous benefits to local communities is less sound. The evaluation of this assumption provides the focus for this inquiry, it follows French sociologist Pierre Bourdieu by considering that ‘one cannot grasp the most profound logic of the social world unless one becomes immersed in the specificity of an empirical reality’ (1993, p. 271). Accordingly, this research contrasted the rhetoric and reality of 2012 Olympic-delivery via an ethnographic inquiry in the Olympic borough of Newham. This location is defined as a ‘non-place’ wherein the majority of the Olympic restructuring and events occurred. This research addresses Olympic-delivery issues of inclusion, exclusion, power relations, ideology and identity, in doing so it argues that the relatively short Olympic-delivery time-frame necessitated a divisive segregation between ‘Olympic’ and ‘non-Olympic’ Newham. Furthermore, it is argued that 2012 Olympic-delivery was orientated towards the needs and goals of Olympic migrants, of various description, rather than enhancing the lives of those living within a community that was rife with crime, poverty and deprivation. Consequently, this research considers that the Olympic milieu disseminated the capitalistic norms and values to global, national and local audiences. The outcome of such processes facilitated a renegotiation of place-identity and place ownership within Newham that was orientated toward attracting a future affluent populace whilst concomitantly vilifying the pre-Games community. This research concludes that such attempts to re-mould Newham into a post-Olympic utopia where prosperous and educated families, to follow the Newham council strap line, ‘live, work and stay’ are based upon the short-sighted assumption that creating an aesthetically pleasing entertainment location is tantamount to creating a desirable location for sustainable family life. Brunel University

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The main design requirements for today's mobile applications are: · high throughput performance. · high energy efficiency. · high programmability. Until now, the choice of platform has often been limited to Application-Specific Integrated Circuits (ASICs), due to their best-of-breed performance and power consumption. The economies of scale possible with these high-volume markets have traditionally been able to hide the high Non-Recurring Engineering (NRE) costs required for designing and fabricating new ASICs. However, with the NREs and design time escalating with each generation of mobile applications, this practice may be reaching its limit. Designers today are looking at programmable solutions, so that they can respond more rapidly to changes in the market and spread costs over several generations of mobile applications. However, there have been few feasible alternatives to ASICs: Digital Signals Processors (DSPs) and microprocessors cannot meet the throughput requirements, whereas Field-Programmable Gate Arrays (FPGAs) require too much area and power. Coarse-grained dynamically reconfigurable architectures offer better solutions for high throughput applications, when power and area considerations are taken into account. One promising example is the Reconfigurable Instruction Cell Array (RICA). RICA consists of an array of cells with an interconnect that can be dynamically reconfigured on every cycle. This allows quite complex datapaths to be rendered onto the fabric and executed in a single configuration - making these architectures particularly suitable to stream processing. Furthermore, RICA can be programmed from C, making it a good fit with existing design methodologies. However the RICA architecture has a drawback: poor scalability in terms of area and power. As the core gets bigger, the number of sequential elements in the array must be increased significantly to maintain the ability to achieve high throughputs through pipelining. As a result, a larger clock tree is required to synchronise the increased number of sequential elements. The clock tree therefore takes up a larger percentage of the area and power consumption of the core. This thesis presents a novel Dynamically Reconfigurable Asynchronous Processor (DRAP), aimed at high-throughput mobile applications. DRAP is based on the RICA architecture, but uses asynchronous design techniques - methods of designing digital systems without clocks. The absence of a global clock signal makes DRAP more scalable in terms of power and area overhead than its synchronous counterpart. The DRAP architecture maintains most of the benefits of custom asynchronous design, whilst also providing programmability via conventional high-level languages. Results show that the DRAP processor delivers considerably lower power consumption when compared to a market-leading Very Long Instruction Word (VLIW) processor and a low-power ARM processor. For example, DRAP resulted in a reduction in power consumption of 20 times compared to the ARM7 processor, and 29 times compared to the TIC64x VLIW, when running the same benchmark capped to the same throughput and for the same process technology (0.13μm). When compared to an equivalent RICA design, DRAP was up to 22% larger than RICA but resulted in a power reduction of up to 1.9 times. It was also capable of achieving up to 2.8 times higher throughputs than RICA for the same benchmarks.

This thesis presents a proof of concept study for the better integration of the electrophysiological and modelling aspects of neuroscience. Members of these two sub-disciplines collaborate regularly, but due to differing resource requirements, and largely incompatible spheres of knowledge, cooperation is often impeded by miscommunication and delays. To reduce the model design time, and provide a platform for more efficient experimental analysis, a rapid iterative model design method is proposed. The main achievement of this work is the development of a rapid model evaluation method based on parameter estimation, utilising a combination of evolutionary algorithms (EAs) and graphics processing unit (GPU) hardware acceleration. This method is the primary force behind the better integration of modelling and laboratorybased electrophysiology, as it provides a generic model evaluation method that does not require prior knowledge of model structure, or expertise in modelling, mathematics, or computer science. If combined with a suitable intuitive and user targeted graphical user interface, the ideas presented in this thesis could be developed into a suite of tools that would enable new forms of experimentation to be performed. The latter part of this thesis investigates the use of excitability-based models as the basis of an iterative design method. They were found to be computationally and structurally simple, easily extensible, and able to reproduce a wide range of neural behaviours whilst still faithfully representing underlying cellular mechanisms. A case study was performed to assess the iterative design process, through the implementation of an excitability-based model. The model was extended iteratively, using the rapid model evaluation method, to represent a vasopressin releasing neuron. Not only was the model implemented successfully, but it was able to suggest the existence of other more subtle cell mechanisms, in addition to highlighting potential failings in previous implementations of the class of neuron.