Search

Native oxide removal prior to poly-Si contact and epitaxial growth of Si is the most critical technology to ensure process and device performances of poly-Si plugs and selective epitaxial growth (SEG) layers for DRAM, flash memory, and logic device. Recently, dry cleaning process for interfacial oxide removal has attracted a world-wide attention due to its superior passivation properties to conventional wet cleaning processes. In this study, we investigated the surface states of Si substrate during and after dry cleaning process, and the role of atomic elements including fluorine and hydrogen on the properties of subsequent deposited silicon layer using SIMS, XPS, and TEM analysis. The controlling of residual fluorine on the Si surface after dry cleaning is a key factor for clean interface. The mechanism of native oxide re-growth caused by residual fluorine after dry cleaning is proposed based on analytical results.

A single-feed wideband circularly polarized Spidron fractal slot antenna with a grooved dielectric resonator is presented. To realize a wideband axial ratio, the circular polarizations of both a Sp...

In this study, the enhancement of the silicon etch rate with the heavy doping of phosphorus and arsenic was studied during cyclic selective epitaxial growth process using batch-type equipment. The reaction between molecular chlorine and heavily doped silicon was stimulated during the initial stage of cyclic SEG process at low temperature lower than 700° to induce voids at the interface. Heavy doping of n-type dopants into active regions also brought about the decrease in the growth rate of SEG process. It was possible to attain a stable process window by the elaborate control of total amount ratio of SiH4/Cl2. The window provided the robust interface between SEG silicon and active regions as well as the selectivity to an oxide layer. Vertical diodes which were realized within the window revealed eligible on- and off-current characteristics for cell switches applicable to next generation cross-point memories.

In this report, we present a cost effective simple innovative approach to fabricate double layer anti-reflection (DLAR) coatings using a single material which can provide high qualities of passivation and anti-reflection property. Two layers of SiN x :H films with different refractive indices were deposited onto p-type c-Si wafer using plasma enhanced chemical vapor deposition reactor by controlling the NH 3 and SiH 4 gas ratio. Refractive indices of top and bottom layers were chosen as 1.9 and 2.3 respectively. The effect of passivation at the interface was investigated by effective carrier lifetime, hydrogen concentration and interface trapped density (D it ) measurements. The optical characteristic was analyzed by reflectance and transmittance measurements. A superior efficiency of 17.61% was obtained for solar cells fabricated with DLAR coating when compared to an efficiency of 17.24% for cells with SLAR coating. Further, J sc and V oc of solar cell with DLAR coating is increased by a value of ~ 1 mA/cm 2 and 4 mV respectively than cell with SLAR coating.

Microlens array (MLA) is microfabricated using Ultra Violet (UV) laser for display device applications. A colorless liquid photopolymer, Norland Optical Adhesive (NOA) 60, is spin-coated and pre-cured via UV light for completing the laser process. The laser energy controlled by a galvano scanner is radiated on the surface of the NOA 60. A rapid thermal volume expansion inside the material creates microlens array when the Gaussian laser energy is absorbed. The fabrication process conditions for various shapes and densities of MLA using a non-contact surface profiler are investigated. Furthermore, we analyze the optical and display characteristics for the Organic Light Emitting Diode (OLED) devices. Optimized condition furnishes the OLED with the enhancement of light emission by 15%. We show that UV laser technique, which is installed with NOA 60 MLA layer, is eligible for improving the performance of the next generation display devices.

Vertical diodes for cross-point phase change memory were realized by selective epitaxial growth (SEG) technique using cyclic chemical vapor deposition method. H2/SiH4/Cl2 cyclic CVD system was introduced in batch-type vertical furnace equipement, replacing conventional single-wafer H2/dichlorosilane/HCl CVD system. It provided excellent capacity of 40 wafers per batch. Selectivity loss which is one of the most crucial features in SEG process for diode application was controlled with both the amount of SiH4 and Cl2 and the period of gas supply, and practical value of selectivity loss was confirmed to be less than 100 in 200-mm wafers. Structural and electrical properties of pn diodes were investigated, and cyclic SEG silicon diode showed more eligible electrical ability to current flow than that of poly-si in terms of forward current and ideality factor as well as lower reverse leakage current.

Germanium (Ge) ion implantation was investigated for crystallinity enhancement during solid phase epitaxial (SPE) regrowth. Electron back-scatter diffraction (EBSD) measurement showed numerical increase of 19% of (100) signal, which might be due to the effect of pre-amorphization implantation (PAI) on silicon layer. On the other hand, electrical property such as off-leakage current of n-channel metal oxide semiconductor (NMOS) transistor degraded in specific regions of wafers. It was confirmed that arsenic (As) atoms were incorporated into channel area during Ge ion implantation. Since the equipment for Ge PAI was using several source gases such as BF3 and AsH3, atomic mass unit (AMU) contamination during PAI of Ge with AMU 74 caused the incorporation of As with AMU 75 which resided in arc-chamber and other parts of the equipment. It was effective to use Ge isotope of AMU 72 to suppress AMU contamination. It was effective to use enriched Ge source gas with AMU 72 in order to improve productivity.

In this letter, a cost-effective vertical diode scheme for next-generation memory devices, including phase-change memories (PCMs), is realized. After the contact formation for diodes with only one mask layer, an amorphous silicon (a-Si) film was deposited within the contacts using SiH4 ramp-up ambient in a conventional batch-type furnace in order to minimize the growth of native oxide. A deposition/etch-back/deposition scheme enabled us to achieve robust vertical diodes without any seams or interfacial oxide layer within the vertical diode pillars. Subsequent annealing at 600 °C provided solid-phase epitaxial alignment of the a-Si layer. An ideality factor revealed that the new scheme provided noticeable crystallinity of the silicon diodes. Moreover, the electrical characteristics of the diodes verified that the scheme was suitable for full operation of PCM devices.

The doping profiles of lightly doped semiconductors are most commonly determined from capacitance-voltage measurements for junction devices. Such C-V measurements work well for large-area devices and lightly doped device, but they are not very suitable for high doping concentrations found in heavily doped devices (1). And the channel region under the MOSFET gate has an additional limitation. The small gate area has very small capacitances that are difficult to measure, making C-V based techniques difficult or impossible. In view of these experimental difficulties, so we tried electrical doping profiling measurement for MOSFET with short gate length and ultra thin oxide thickness and checked an agreement with ISE simulation results.

Background and objective The role of nitric oxide (NO) needs to be further clarified in allergic inflammation. This study was designed to investigate the relationships between NO metabolites and eosinophil count, eosinophil cationic protein (ECP), interleukin (IL)-5 in induced sputum from asthmatics. Methods Hypertonic saline-induced sputum was obtained in 25 asthmatic subjects, among which 13 patients were examined before and after anti-asthmatic medications including steroid preparations. Ten normal subjects were enrolled as controls. Fresh expectorated sputum separated from saliva was treated with equal volume of dithiothreitol 0.1%, cytospined for cell count, and the supernatant was collected for biochemical assay. NO metabolites were assayed by using modified Griess reaction. ECP was measured by fluoroimmunoassay, and detected IL-5 by a sandwich ELISA. Results Asthmatic subjects, compared with controls, had significantly higher concentration of NO metabolites (1035.4 ± 125.3 vs 557.2 ± 101.5 μmol/L, P

The structural, electrical properties of (Ba,Sr)TiO3[BSTO]/RuO2 thin films were controlled by the addition of amorphous BSTO layers between crystalline BSTO film and RuO2 substrate. We prepared BSTO films with double-layered structure, that is, amorphous layers deposited at 60 °C and crystalline films. Crystalline films were prepared at 550 °C on amorphous BSTO layers. The thickness of amorphous layers was varied from 0 to 170 nm. During the deposition of crystalline films, the crystallization of amorphous layers occurred and the structure was changed to circular while crystalline BSTO films showed columnar structure. Due to insufficient annealing effect, amorphous BSTO phase was observed when amorphous layers exceeded 30 nm. Amorphous BSTO layer could also prevent the formation of oxygen deficient region in RuO2 surface. Leakage current of total BSTO films decreased with increasing amorphous layer thickness due to structural modifications. Dielectric constant showed maximum value of 343 when amorphous la...

In this paper, current-voltage-temperature (I-V-T) characteristics of vertical diodes realized by different selective epitaxial growth techniques have been investigated. Diodes by the batch-type cyclic SEG process at low temperature have shown eligible performances for vertical switches, including ideality factor of 1.08, off-current of 1.0×10−12 A and on/off-ratio of 2.4×108. The optimization of crystallographic defects and series resistance is expected to be the most critical for the performances of vertical diodes for next generation memories.

Summary Background Asthma can frequently be induced or exacerbated by respiratory viral infections. Oxidative stress might also play an essential role in the pathogenesis of allergic airway diseases, indicating that antioxidant therapy may have a potential effect in controlling allergic airway diseases. Recent studies showed that 5-aminoimidazole-4-carboxamide-1-β-4-ribofuranoside (AICAR) has the potential ability to modulate NADPH oxidase activity, indicating the antioxidant activity of AICAR. This study investigated the inhibitory effects of AICAR as an anti-inflammatory modulator on allergic airway inflammation in murine animal models. Methods The anti-inflammatory effects of AICAR were evaluated in two experimental asthma models: (1) an ovalbumin (OVA)-induced experimental asthma model and (2) an OVA plus polyinosinic-polycytidylic acid [poly (I:C)]-induced experimental asthma model to mimic respiratory viral infections. The inhibitory effects of AICAR in poly (I:C)-mediated signalling for NF-κB activation and production of TNF-α were analysed in vitro. Results AICAR was shown to have a marginal inhibitory effect in an OVA-induced asthma model. Interestingly, AICAR significantly attenuated poly (I:C)-induced airway hyperresponsiveness and airway inflammation, as shown by the attenuation of the influx of total inflammatory cells and soluble products into bronchoalveolar lavage fluid, such as macrophages, eosinophils, IL-5, IL-13, TNF-α and IFN-γ. AICAR also significantly reduced the serum levels of OVA-specific IgE and IgG2a antibodies. Histologic and flow cytometric studies showed that AICAR inhibited poly (I:C)-induced lung inflammation and the infiltration of CD11b+CD11c+ dendritic cells into the lung. Moreover, AICAR effectively inhibited poly (I:C)-mediated activation of NF-κB and the production of TNF-α. Conclusion These findings suggest that AICAR may be a novel immunomodulator with promising beneficial effects for the treatment of respiratory viral infection in airway allergic diseases.

In this article, we report improved results of 4-bit double SONOS memories (DSMs) with 4-storage nodes through the optimization of ONO layer thicknesses for front and back sides. They show more balanced characteristics between the front and back channels, higher VTH shifts above 2.4V, larger read margins above 1.6V, better endurance, and longer retention time than our previous results. In addition, we also propose and demonstrate a highly scaled 4-bit DSM using multi-level technology. The VTH shifts above 4V splitting into 4 levels without noticeable interferences are achieved. Each nodes show clear 4 levels with good retention

Abnormal gate oxide thickening at active edge (GOTAE) has been investigated in dynamic random access memories (DRAMs) with SiN-lineared shallow trench isolation (STI). 1% of gaseous HCl, which is added during dry oxidation, plays a major role in inducing abnormal GOTAE by the mechanical interaction with thin SiN layers in STI. Other structural parameters, such as the thickness of trench sidewall oxide, liner SiN and sacrificial oxide, are believed to influence the amount of oxide thickening. In order to avoid abnormal GOTAE, wet oxidation is introduced and shown to be effective in suppressing it. Electrical properties, which are susceptible to the extent of GOTAE, are also presented in this paper.

P+ to p+ isolation degradation that causes DRAM standby current failure under burn-in mode operation is investigated. Although the isolation of the test devices dose not show any degradation or weakness in conventional electrical characterization, it is found that the degradation can be observed by a carrier injection method. Using the simple carrier injection method to simulate the real operating condition of a DRAM chip, a potential problem of the isolation degradation can be easily found, which cannot be screened by conventional electrical measurement.

In this study, an attempt is made to provide a framework to assess and improve metal–oxide–semiconductor field-effect transistor (MOSFET) reliability from the early stage of the design to the completion of the product. A small gate area has very small capacitances that are difficult to measure, making capacitance–voltage (C–V) based techniques difficult or impossible. In view of these experimental difficulties, we tried electrical doping profiling measurement for MOSFET with short gate length, ultra thin oxide thickness and asymmetric source/drain structure and checked the agreement with simulation result. We could get the effective mobility by simple drain current versus drain bias voltage measurement. The calculated effective mobility was smaller than expected value and we explained some reasons. An accurate effective mobility for asymmetric source–drain junction transistor was successfully extracted by using the split C–V technique, with the capacitance measured between the gate and source–drain and between the gate and the substrate.

Solid phase epitaxy (SPE) techniques have been studied to realize stacked static random memory (SRAM) devices. Among the candidates including epitaxial lateral overgrowth (ELO) and laser epitaxial growth (LEG) techniques, SPE is the most stable and cost-effective scheme since it is fulfilled by the deposition of amorphous silicon layers and the subsequent low temperature annealing using conventional furnace equipment which has been used for several decades in semiconductor fabrication. We introduced silicon seeds for the epitaxial realignment of amorphous silicon within the contact window by the selective epitaxial growth (SEG) of single-crystalline silicon. The role of process variables associated with channel silicon deposition on SPE was investigated. The efficiency of SPE was quantified by electron back-scatter diffraction (EBSD) measurement, which visualizes the fraction of the orientation in a channel silicon layer. SiH4 ambient during the ramp-up stage in the deposition of amorphous silicon layers showed superior epitaxial realignment to N2 ambient, which was mainly due to the suppression of interfacial layer formation. Electrical characteristics such as on-current distribution and static noise margin indicated SPE to be feasible for high-density stacked SRAM application.

Selectivity control in silicon selective epitaxial growth (SEG) for deep contact patterns, which is one of the key processes for silicon-based stacked devices and cell switches for next generation memories, was studied. Absolute values of selectivity loss during silicon SEG using the most popular H2/dichlorosilane (DCS)/HCl gas system were evaluated using a commercialized inspection tool in 200 mm wafers with real contact patterns. It was revealed that HCl/(DCS+HCl) ratio and the contact structure played a crucial role in suppressing selectivity loss. The number of selectivity losses in an entire wafer was less than 100 when the HCl/(DCS+HCl) ratio was larger than 0.41. The vertical pn diode prepared using the silicon SEG process with elaborate selectivity control showed more remarkable electrical abilities to accommodate current flow than polycrystalline silicon (poly-Si), including the ideality factor and swing, and reverse leakage current.

not Available.

not Available.

We have investigated a short channel (L μm) effect on an electrical reliability in low temperature poly-Si (LTPS) thin film transistor (TFT) employing excimer laser annealing (ELA). The decrease of threshold voltage due to the drain induced barrier lowering (DIBL) is observed in p-type poly-Si TFT without lightly doped drain (LDD). In the n-type poly-Si TFT with LDD, the threshold voltage is slightly decreased when a large drain bias is applied. The field effect mobility is observed on various channel length and LDD. The series resistance due to the LDD in the short channel LTPS is decreased the field effect mobility. The operating temperature dependence of the electrical characteristics is investigated. As the temperature is increase, the poly-Si TFT's characteristics is improved due to the increase the thermally activated carriers. We have investigated a reliability of short channel poly-Si TFT. The degradation of short channel poly-Si TFT under the hot carrier stress is dominant to interface state.

(Ba, Sr)TiO3 (BST) films are deposited on 8-inch wafers by the metal organic chemical vapor deposition (MOCVD) technique at a temperature as low as 400°C to obtain conformal step coverage and prevent oxidation of the diffusion barrier of simple stacked capacitors. The problems of low temperature process (formation of protrusions, titanium deficiency, severe thickness deviation) could be successfully overcome by proper modification of the CVD system and process conditions. Retrofitting the vaporizer to obtain flash evaporation of the liquid chemical source and introducing N2O gas as an oxidant were highly effective for reducing the thickness deviation and titanium deficiency. The Pt/BST/Pt capacitor with BST films deposited at 400°C and post-annealed at 700°C for 30 min under nitrogen ambient shows excellent electrical properties (T o x∼6.6 Å, J∼1×10-7 A/cm2 @±1 V), which are satisfactory for application to high density dynamic random access memory (DRAM) capacitors beyond 256 Mbit generation.

The electrical degradation of (Ba, Sr)TiO3 [BST] thin films as a function of the film thickness was investigated. BST thin films with various thickness were deposited on Pt/Ti/SiO2/Si substrates by in-situ RF magnetron sputtering. It was found that the electrical properties degraded markedly as the thickness of the films decreased. Electrical properties such as the leakage current and the dielectric constant are closely related to the surface morphology, in particular, the grain size of the films. The existence of an interfacial layer between the BST film and the Pt bottom electrode was confirmed by HRTEM. The interfacial layer appeared to have crystallinity different from both the BST thin film and the Pt bottom electrode which resulted in variation of the interfacial states between BST and Pt. As the thickness of the BST films decreased from 300 nm to 50 nm, the thickness of the interfacial layer increased from 9.5 nm to 11 nm. The dielectric constant of the interfacial layer calculated from its measured overall capacitance and thickness, confirmed by HRTEM, was about 30. This low-dielectric-constant interfacial layer has been shown to affect the electrical degradation of BST thin films with decreasing thickness.