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We have demonstrated the scalability of a process previously dubbed as Ge “touchdown” on Si to substantially reduce threading dislocations below 10 7 /cm 2 in a Ge film grown on a 2 inch-diameter chemically oxidized Si substrate. This study also elucidates the overall mechanism of the touchdown process. The 1.4 nm thick chemical oxide is first formed by immersing Si substrates in a solution of H 2 O 2 and H 2 SO 4 . Subsequent exposure to Ge flux creates 3 to 7 nm-diameter voids in the oxide at a density greater than 10 11 /cm 2 . Comparison of data taken from many previous studies and ours shows an exponential dependence between oxide thickness and inverse temperature of void formation. Additionally, exposure to a Ge or Si atom flux decreases the temperature at which voids begin to form in the oxide. These results strongly suggest that Ge actively participates in the reaction with SiO 2 in the void formation process. Once voids are created in the oxide under a Ge flux, Ge islands selectively nucleate within the void openings on the newly exposed Si. Island nucleation and growth then compete with the void growth reaction. At substrate temperatures between 823 and 1053 K, nanometer size Ge islands that nucleate within the voids continue to grow and coalesce into a continuous film over the remaining oxide. Coalescence of the Ge islands is believed to result in the creation of stacking faults in the Ge film at a density of 5 × 10 7 /cm 2 . Additionally, coalescence results in films of 3 µm thickness having a root-mean-square roughness of 8 to 10 nm. We have found that polishing the films with dilute H 2 O 2 results in roughness values below 0.5 nm. However, stacking faults originating at the Ge–SiO 2 interface and terminating at the Ge surface are polished at a slightly reduced rate, and show up as 1 to 2 nm raised lines on the polished Ge surface. These lines are then transferred into the subsequent growth morphology of GaAs deposited by metal-organic chemical vapor deposition. Room temperature photoluminescence shows that films of GaAs grown on Ge-on-oxidized Si have an intensity that is 20 to 25% compared to the intensity from GaAs grown on commercial Ge or GaAs substrates. Cathodoluminescence shows that nonradiative defects occur in the GaAs that spatially correspond to the stacking faults terminating at the Ge surface. The exact nature of these nonradiative defects in the GaAs is unknown, however, GaAs grown on annealed samples of Ge-on-oxidized Si, whereby annealing removes the stacking faults, have photoluminescence intensity that is comparable to GaAs grown on a GaAs substrate.

We describe efforts to epitaxially integrate GaAs with Si, using thin, relaxed Ge layers. The Ge films are deposited by molecular beam epitaxy using a self-assembled, selective-area growth technique, where atomic Ge etches an SiO 2 mask layer and then grows from pores extending to the Si substrate. The resulting Ge film coalesces over the SiO 2 mask and is planarized, using H 2 O 2 -based chemical–mechanical polishing. We subsequently deposit a GaAs/AlAs heterostructure on the polished Ge on Si substrate by metal-organic vapor phase epitaxy. While the initial Ge films were completely relaxed and dislocation-free, they contain a high density of stacking faults that propagate through the GaAs/AlAs heterostructure. These stacking faults create phase domains that appear as non-radiative recombination centers in cathodoluminescence images. Further development of two-step Ge epitaxy with an anneal near the Ge melting point eliminates stacking faults in the Ge, but decomposes the SiO 2 mask allowing threading dislocations to form and propagate through the GaAs/AlAs heterostructure. We discuss our strategy to prevent the loss of the SiO 2 mask and thus reduce threading dislocations.

Demand for integration of optoelectronic functionality (e.g., optical interconnects) with silicon complementary metal oxide semiconductor (CMOS) technology has for many years motivated the investigation of low temperature (∼ 450°C) germanium deposition processes that may be integrated in to the back-end CMOS process flow. A common challenge to improving the germanium quality is the thermal budget of the in-situ bake, which is used to reduce defect forming oxygen and carbon surface residues. Typical cleaning temperatures to remove significant concentrations of oxygen and carbon have been reported to be approximately 750°C for thermal hydrogen bakes in standard chemical vapor deposition chambers. Germanium device performance using lower peak in-situ cleans (i.e., ∼450°C) has been hampered by additional crystal defectivity, although epitaxy is possible with out complete removal of oxygen and carbon at lower temperatures.Plasma enhanced chemical vapor deposition (PECVD) is used to reduce the processing temperature. Hydrogen plasma assisted in-situ surface preparation of epitaxy has been shown to reduce both carbon and oxygen concentrations and enable epitaxial growth at temperatures as low as ∼150°C. The hydrogen is believed to help produce volatile Si-O and H2O species in the removal of oxygen, although typically this is not reported to occur rapidly enough to completely clear the surface of all oxygen until ∼550°C. In this paper, we describe the use of an in-situ argon/germane high density plasma to help initiate germanium epitaxy on silicon using a peak temperature of approximately 460°C. Germanium is believed to readily break Si-O bonds to form more volatile Ge-O, therefore, argon/germane plasmas offer the potential to reduce the necessary in-situ clean temperature while obtaining similar results as hydrogen in-situ cleans. To the authors knowledge this report is also the first demonstration of germanium epitaxy on silicon using this commercially available high density plasma chamber configuration instead of, for example, remote or electron cyclotron resonance configurations.