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This paper advocates for an intertwined design of the dense linear algebra software stack that breaks down the strict barriers between the high-level, blocked algorithms in LAPACK (Linear Algebra PACKage) and the low-level, architecture-dependent kernels in BLAS (Basic Linear Algebra Subprograms). Specifically, we propose customizing the GEMM (general matrix multiplication) kernel, which is invoked from the blocked algorithms for relevant matrix factorizations in LAPACK, to improve performance on modern multicore processors with hierarchical cache memories. To achieve this, we leverage an analytical model to dynamically adapt the cache configuration parameters of the GEMM to the shape of the matrix operands. Additionally, we accommodate a flexible development of architecture-specific micro-kernels that allow us to further improve the utilization of the cache hierarchy. Our experiments on two platforms, equipped with ARM (NVIDIA Carmel, Neon) and x86 (AMD EPYC, AVX2) multi-core processors, demonstrate the benefits of this approach in terms of better cache utilization and, in general, higher performance. However, they also reveal the delicate balance between optimizing for multi-threaded parallelism versus cache usage.

En el presente trabajo se evalúa la utilidad clínica del análisis cuantitativo del bufly coat mediante el Sistema QBC-V para su uso en Medicina Veterinaria canina. Se compara el Sistema QBC-V frente al método manual de referencia en 100 muestras de sangre de perro. Los resultados obtenidos indican que existe una correlación muy elevada para el valor hematocrito y el recuento de leucocitos y granulocitos (neutrófilos, eosinófilos y basófilos), elevada para el recuento de agranulocitos (linfocitos y monocitos) y baja para las plaquetas. This study evaluates the clinical utility value of the "buffy coat" quantitative analysis by means of the QBC-V system for canine Veterinary Medicine purposes. Tbe QBC-V system is compared with the reference manual method in the blood samples of lOOdogs. Tbe results obtained shaw that the height of the "buffy coat" correlates very highly with the haematocrit value, totalleucocyte and granulocyte (neutropbils, eosinophils and basophils) count, highly with the agranulocyte (limphocytes and monocytes) count and lowly with the platelets count.

The TensorFlow framework was designed since its inception to provide multi-thread capabilities, extended with hardware accelerator support to leverage the potential of modern architectures. The amount of parallelism in current versions of the framework can be selected at multiple levels (intra- and inter-paralellism) under demand. However, this selection is fixed, and cannot vary during the execution of training/inference sessions. This heavily restricts the flexibility and elasticity of the framework, especially in scenarios in which multiple TensorFlow instances co-exist in a parallel architecture. In this work, we propose the necessary modifications within TensorFlow to support dynamic selection of threads, in order to provide transparent malleability to the infrastructure. Experimental results show that this approach is effective in the variation of parallelism, and paves the road towards future co-scheduling techniques for multi-TensorFlow scenarios. Instituto de Investigación en Informática

The TensorFlow framework was designed since its inception to provide multi-thread capabilities, extended with hardware accelerator support to leverage the potential of modern architectures. The amount of parallelism in current versions of the framework can be selected at multiple levels (intra- and inter-paralellism) under demand. However, this selection is fixed, and cannot vary during the execution of training/inference sessions. This heavily restricts the flexibility and elasticity of the framework, especially in scenarios in which multiple TensorFlow instances co-exist in a parallel architecture. In this work, we propose the necessary modifications within TensorFlow to support dynamic selection of threads, in order to provide transparent malleability to the infrastructure. Experimental results show that this approach is effective in the variation of parallelism, and paves the road towards future co-scheduling techniques for multi-TensorFlow scenarios., Instituto de Investigación en Informática

The minimum distance of a linear code is a key concept in information theory. Therefore, the time required by its computation is very important to many problems in this area. In this paper, we introduce a family of implementations of the Brouwer-Zimmermann algorithm for distributed-memory architectures for computing the minimum distance of a random linear code over F2. Both current commercial and public-domain software only work on either unicore architectures or shared-memory architectures, which are limited in the number of cores/processors employed in the computation. Our implementations focus on distributed-memory architectures, thus being able to employ hundreds or even thousands of cores in the computation of the minimum distance. Our experimental results show that our implementations are much faster, even up to several orders of magnitude, than current implementations widely used nowadays.

Cache timing attacks use shared caches in multi-core processors as side channels to extract information from victim processes. These attacks are particularly dangerous in cloud infrastructures, in which the deployed countermeasures cause collateral effects in terms of performance loss and increase in energy consumption. We propose to monitor the victim process using an independent monitoring (detector) process, that continuously measures selected Performance Monitoring Counters (PMC) to detect the presence of an attack. Ad-hoc countermeasures can be applied only when such a risky situation arises. In our case, the victim process is the AES encryption algorithm and the attack is performed by means of random encryption requests. We demonstrate that PMCs are a feasible tool to detect the attack and that sampling PMCs at high frequencies is worse than sampling at lower frequencies in terms of detection capabilities, particularly when the attack is fragmented in time to try to be hidden from detection.

En este artículo se presenta una implementación de BLAS, basada en la biblioteca BLIS, para AMPs. La evaluación de esta versión consciente de la asimetría se lleva a cabo a través de tres operaciones comunes de la biblioteca LAPACK: la factorización LU, la factorización Cholesky y la reducción a la forma tridiagonal. Los tests iniciales que emplean la implementación para AMPs directamente muestran las mejoras obtenidas con la adaptación del software al utilizarlo como base de las operaciones LAPACK, obteniendo hasta un 90% del rendimiento máximo esperado. Además, estas mejoras se ven incrementadas al combinar la versión diseñada para AMPs con un runtime, en cuyo caso se obtienen rendimientos hasta un 30% superiores respecto a la utilización directa de la versión para AMPs.

The minimum distance of an error-correcting code is an important concept in information theory. Hence, computing the minimum distance of a code with a minimum computational cost is crucial to many problems in this area. In this article, we present and assess a family of implementations of both the brute-force algorithm and the Brouwer-Zimmermann algorithm for computing the minimum distance of a random linear code over that are faster than current implementations, both in the commercial and public domain. In addition to the basic sequential implementations, we present parallel and vectorized implementations that produce high performances on modern architectures. The attained performance results show the benefits of the developed optimized algorithms, which obtain remarkable improvements compared with state-of-the-art implementations widely used nowadays.

In this paper we describe HeSP, a complete simulation framework to study a general task scheduling-partitioning problem on heterogeneous architectures, which treats recursive task partitioning and scheduling decisions on equal footing. Considering recursive partitioning as an additional degree of freedom, tasks can be dynamically partitioned or merged at runtime for each available processor type, exposing additional or reduced degrees of parallelism as needed. Our simulations reveal that, for a specific class of dense linear algebra algorithms taken as a driving example, simultaneous decisions on task scheduling and partitioning yield significant performance gains on two different heterogeneous platforms: a highly heterogeneous CPU-GPU system and a low-power asymmetric big.LITTLE ARM platform. The insights extracted from the framework can be further applied to actual runtime task schedulers in order to improve performance on current or future architectures and for different task-parallel codes.

Dense linear algebra libraries, such as BLAS and LAPACK, provide a relevant collection of numerical tools for many scientific and engineering applications. While there exist high performance implementations of the BLAS (and LAPACK) functionality for many current multi-threaded architectures,the adaption of these libraries for asymmetric multicore processors (AMPs)is still pending. In this paper we address this challenge by developing an asymmetry-aware implementation of the BLAS, based on the BLIS framework, and tailored for AMPs equipped with two types of cores: fast/power hungry versus slow/energy efficient. For this purpose, we integrate coarse-grain and fine-grain parallelization strategies into the library routines which, respectively, dynamically distribute the workload between the two core types and statically repartition this work among the cores of the same type. Our results on an ARM big.LITTLE processor embedded in the Exynos 5422 SoC, using the asymmetry-aware version of the BLAS and a plain migration of the legacy version of LAPACK, experimentally assess the benefits, limitations, and potential of this approach.

Asymmetric processors have emerged as an appealing technology for severely energy-constrained environments, especially in the mobile market where heterogeneity in applications is mainstream. In addition, given the growing interest on ultra low-power architectures for high performance computing, this type of platforms are also being investigated in the road towards the implementation of energy- efficient high-performance scientific applications. In this paper, we propose a first step towards a complete implementation of the BLAS interface adapted to asymmetric ARM big.LITTLE processors, analyzing the trade-offs between performance and energy efficiency when compared to existing homogeneous (symmetric) multi-threaded BLAS implementations. Our experimental results reveal important gains in performance while maintaining the energy efficiency of homogeneous solutions by efficiently exploiting all the resources of the asymmetric processor., Presented at HiPEAC 2015, Amsterdam. Foundation of the Asymmetric BLIS implementation

Dealing with asymmetry in the architecture opens a plethora of questions from the perspective of scheduling task-parallel applications, and there exist early attempts to address this problem via ad-hoc strategies embedded into a runtime framework. In this paper we take a different path, which consists in addressing the complexity of the problem at the library level, via a few asymmetry-aware fundamental kernels, hiding the architecture heterogeneity from the task scheduler. For the specific domain of dense linear algebra, we show that this is not only possible but delivers much higher performance than a naive approach based on an asymmetry-oblivious scheduler. Furthermore, this solution also outperforms an ad-hoc asymmetry-aware scheduler furnished with sophisticated scheduling techniques.

The road towards Exascale Computing requires a holistic effort to address three different challenges simultaneously: high performance, energy efficiency, and programmability. The use of runtime task schedulers to orchestrate parallel executions with minimal developer intervention has been introduced in recent years to tackle the programmability issue while maintaining, or even improving, performance. In this paper, we enhance the SuperMatrix runtime task scheduler integrated in the libflame library in two different directions that address high performance and energy efficiency. First, we extend the runtime by accom- modating hybrid parallel executions and managing task priorities for dense linear algebra operations, with remarkable performance improvements. Second, we introduce techniques to reduce energy consumption during idle times inherent to parallel executions, attaining important energy savings. In addition, we propose a power consumption model that can be leveraged by runtime task schedulers to make decisions based not only on performance but also on energy considerations., This research was supported by project CICYT TIN2011-23283 and FEDER, and by the EU-FET grant 'EXA2GREEN' 318793. Francisco D. Igual was supported by project TIN2012-32180.

The arrival of multicore architectures has generated an interest in reformulating dense matrix computations as algorithms-by-blocks, where submatrices are units of data and computations with those blocks are units of computation. Rather than directly executing such an algorithm, a directed acyclic graph is generated at runtime that is then scheduled by a runtime system such as SuperMatrix. The benefit is a clear separation of concerns between the library and the heuristics for scheduling. In this paper, we show that this approach can be taken one step further using the same methodology and an ad hoc runtime to map algorithms-by-blocks to small clusters. With no change to the library code, and the application that uses it, the computational power of such small clusters can be utilized. An impressive performance on a number of small clusters is reported. As a proof of the flexibility of the solution, we report performance results on accelerated clusters based on graphics processors. We believe this to be a possible step towards programming many-core architectures, as demonstrated by a port of the solution to Intel's Single-chip Cloud Computer (Intel, Santa Clara, CA, USA). Copyright © 2012 John Wiley & Sons, Ltd.

We investigate the performance of the routines in LAPACK and the Successive Band Reduction (SBR) toolbox for the reduction of a dense matrix to tridiagonal form, a crucial preprocessing stage in the solution of the symmetric eigenvalue problem, on general-purpose multi-core processors. In response to the advances of hardware accelerators, we also modify the code in SBR to accelerate the computation by off-loading a significant part of the operations to a graphics processor (GPU). Performance results illustrate the parallelism and scalability of these algorithms on current high-performance multi-core architectures.

We present several algorithms to compute the solution of a linear system of equations on a graphics processor (GPU), as well as general techniques to improve their performance, such as padding and hybrid GPU-CPU computation. We compare single and double precision performance of a modern GPU with unified architecture, and show how iterative refinement with mixed precision can be used to regain full accuracy in the solution of linear systems, exploiting the potential of the processor for single precision arithmetic. Experimental results on a GTX280 using CUBLAS 2.0, the implementation of BLAS for NVIDIA® GPUs with unified architecture, illustrate the performance of the different algorithms and techniques proposed.

We combine two high-level application programming interfaces to solve large-scale linear systems with the data stored on disk using current graphics processors. The result is a simple yet powerful tool that enables a fast development of object-oriented codes, implemented as MATLAB M-scripts, for linear algebra operations. The approach enhances the programmability of the solutions in this problem domain while unleashing the high performance of graphics processors. Experimental results are reported from OCTAVE, linked with the implementation of BLAS by NVIDIA, and executed on a G80 processor. Se combinan dos APIs de alto nivel para la resolución de sistemas lineales de gran escala con los datos almacenados en disco, mediante el uso de procesadores gráficos de última generación. El resultado es una herramienta simple, aunque de gran potencia, que permite el rápido desarrollo de códigos orientados a objetos, implementados como M-scripts, para operaciones de álgebra lineal. Nuestra propuesta mejora la facilidad de programación para este tipo de problemas, y a la vez aprovecha el elevado rendimiento de los procesadores gráficos. Los resultados experimentales han sido extraidos de OCTAVE, enlazado con la implementación de BLAS de NVIDIA, y ejecutados sobre un procesador G80

We present several algorithms to compute the solution of a linear system of equations on a GPU, as well as general techniques to improve their performance, such as padding and hybrid GPU-CPU computation. We also show how iterative refinement with mixed-precision can be used to regain full accuracy in the solution of linear systems. Experimental results on a G80 using CUBLAS, the implementation of BLAS for NVIDIA(R)GPUs with unified architecture, are given to illustrate the performance of the different algorithms and techniques proposed El presente informe describe diferentes algoritmos para calcular la solución de un sistema lineal sobre una GPU, así como técnicas generales para mejorar su renidimento, como padding y técnicas híbridas CPU-GPU. Además, se hace uso de técnicas de refinamiento iterativo con precisión mixta, para conseguir mayor precisión en la solución obtenida. Se incluyen resultados experimentales sobre el procesador G80 haciendo uso de CUBLAS, la implementación de BLAS desarrollada por NVIDIA(R) para GPUs con arquitectura unificada

We propose two high-level application programming interfaces (APIs) to use a graphics processing unit (GPU) as a coprocessor for dense linear algebra operations. Combined with an extension of the FLAME API and an implementation on top of NVIDIA CUBLAS, the result is an efficient and user-friendly tool to design, implement, and execute dense linear algebra operations on the current generation of NVIDIA graphics processors, of wide-appeal to scientists and engineers. As an application of the developed APIs, we implement and evaluate the performance of three different variants of the Cholesky factorization El artículo presenta dos interfaces de programación (APIs) de alto nivel para el uso de unidades de procesamiento gráfico (GPU) como coprocesadores para la realización de operaciones de álgebra lineal densa. En combinación con una extensión de la interfaz de FLAME y una implementación basada en la biblioteca CUBLAS de NVIDIA, el resultado es una herramienta eficiente y de fácil uso para diseñar, implementar y ejecutar operaciones de álgebra lineal densa sobre la última generación de procesadores gráficos de NVIDIA. Como aplicación de la interfaz desarrollada, se implementa y evalúa el rendimiento de tres variantes de la factorización de Cholesky

The increase in performance of the last generations of graphics processors (GPUs) has made this class of platform a coprocessing tool with remarkable success in certain types of operations. In this paper we evaluate the performance of the Level 3 operations in CUBLAS, the implementation of BLAS for NVIDIA(R) GPUs with unified architecture. From this study, we gain insights on the quality of the kernels in the library and we propose several alternative implementations that are competitive with those in CUBLAS. Experimental results on a GeForce 8800 Ultra compare the performance of CUBLAS and the new variants El incremento en las prestaciones de las últimas generaciones de procesadores gráficos (GPUs), ha convertido a este tipo de plataformas en herramientas de coprocesamiento con notable éxito frente a cierto tipo de aplicaciones. En el presente artículo, se evalua el rendimiento de las operaciones de Nivel 3 de CUBLAS, la implementación de BLAS desarrollada por NVIDIA(R) para sus procesadores gráficos con arquitectura unificada. A partir del estudio, se extraen conclusiones acerca de la calidad de las implementaciones de la biblioteca, y se proponen implementaciones alternativas que mejoran el rendimiento de las implementaciones originales. Los resultados experimentales sobre una GeForce 8800 Ultra comparaen el rendimiento de CUBLAS y las nuevas variantes propuestas

The increase in performance of the last generations of graphics processors (GPUs) has made this class of hardware a coprocessing platform of remarkable success in certain types of operations. In this paper we evaluate the performance of linear algebra and image processing routines, both on classical and unified GPU architectures and traditional processors (CPUs). From this study, we gain insights on the properties that make an algorithm likely to deliver high performance on a GPU El aumento de prestaciones de las últimas generaciones de procesadores gráficos (GPUs) ha convertido a este tipo de hardware en una plataforma de coprocesamiento de considerable éxito para cierto tipo de aplicaciones. En el presente artículo, se evalua el rendimiento de rutinas de álgebra lineal y procesamiento de imágenes, tanto en arquitecuturas gráficas clásicas como unificadas, así como sobre procesadores de carácter general (CPUs). A partir de dicho estudio, se extraen las propiedades que hacen de un algoritmo candidato a obtener elevado rendimiento al ser ejecutado sobre una GPU

We propose two high-level application programming interfaces (APIs) to use a graphics processing unit (GPU) as a coprocessor for dense linear algebra operations. Combined with an extension of the FLAME API and an implementation on top of NVIDIA CUBLAS, the result is an efficient and user-friendly tool to design, implement, and execute dense linear algebra operations on the current generation of NVIDIA graphics processors, of wide-appeal to scientists and engineers. As an application of the developed APIs, we implement and evaluate the performance of three different variants of the Cholesky factorization El artículo presenta dos interfaces de programación (APIs) de alto nivel para el uso de unidades de procesamiento gráfico (GPU) como coprocesadores para la realización de operaciones de álgebra lineal densa. En combinación con una extensión de la interfaz de FLAME y una implementación basada en la biblioteca CUBLAS de NVIDIA, el resultado es una herramienta eficiente y de fácil uso para diseñar, implementar y ejecutar operaciones de álgebra lineal densa sobre la última generación de procesadores gráficos de NVIDIA. Como aplicación de la interfaz desarrollada, se implementa y evalúa el rendimiento de tres variantes de la factorización de Cholesky

The increase in performance of the last generations of graphics processors (GPUs) has made this class of hardware a coprocessing platform of remarkable success in certain types of operations. In this paper we evaluate the performance of linear algebra and image processing routines, both on classical and unified GPU architectures and traditional processors (CPUs). From this study, we gain insights on the properties that make an algorithm likely to deliver high performance on a GPU El aumento de prestaciones de las últimas generaciones de procesadores gráficos (GPUs) ha convertido a este tipo de hardware en una plataforma de coprocesamiento de considerable éxito para cierto tipo de aplicaciones. En el presente artículo, se evalua el rendimiento de rutinas de álgebra lineal y procesamiento de imágenes, tanto en arquitecuturas gráficas clásicas como unificadas, así como sobre procesadores de carácter general (CPUs). A partir de dicho estudio, se extraen las propiedades que hacen de un algoritmo candidato a obtener elevado rendimiento al ser ejecutado sobre una GPU

We combine two high-level application programming interfaces to solve large-scale linear systems with the data stored on disk using current graphics processors. The result is a simple yet powerful tool that enables a fast development of object-oriented codes, implemented as MATLAB M-scripts, for linear algebra operations. The approach enhances the programmability of the solutions in this problem domain while unleashing the high performance of graphics processors. Experimental results are reported from OCTAVE, linked with the implementation of BLAS by NVIDIA, and executed on a G80 processor. Se combinan dos APIs de alto nivel para la resolución de sistemas lineales de gran escala con los datos almacenados en disco, mediante el uso de procesadores gráficos de última generación. El resultado es una herramienta simple, aunque de gran potencia, que permite el rápido desarrollo de códigos orientados a objetos, implementados como M-scripts, para operaciones de álgebra lineal. Nuestra propuesta mejora la facilidad de programación para este tipo de problemas, y a la vez aprovecha el elevado rendimiento de los procesadores gráficos. Los resultados experimentales han sido extraidos de OCTAVE, enlazado con la implementación de BLAS de NVIDIA, y ejecutados sobre un procesador G80

We present several algorithms to compute the solution of a linear system of equations on a GPU, as well as general techniques to improve their performance, such as padding and hybrid GPU-CPU computation. We also show how iterative refinement with mixed-precision can be used to regain full accuracy in the solution of linear systems. Experimental results on a G80 using CUBLAS, the implementation of BLAS for NVIDIA(R)GPUs with unified architecture, are given to illustrate the performance of the different algorithms and techniques proposed El presente informe describe diferentes algoritmos para calcular la solución de un sistema lineal sobre una GPU, así como técnicas generales para mejorar su renidimento, como padding y técnicas híbridas CPU-GPU. Además, se hace uso de técnicas de refinamiento iterativo con precisión mixta, para conseguir mayor precisión en la solución obtenida. Se incluyen resultados experimentales sobre el procesador G80 haciendo uso de CUBLAS, la implementación de BLAS desarrollada por NVIDIA(R) para GPUs con arquitectura unificada

En las últimas décadas, el avance de los algoritmos de Aprendizaje Automático (Machine Learning, ML) ha despertado el interés en la búsqueda de estrategias que logren acelerar los procesos de entrenamiento e inferencia típicos de este ámbito, especialmente cuando éstos surgen en servidores con un elevado grado de paralelismo, complejidad y heterogeneidad. Típicamente, estos procesos se realizan a través de entornos de trabajo (frameworks) de propósito específico tales como Tensoflow, Keras, Caffe o Pytorch. A día de hoy, Tensorflow es uno de los frameworks más utilizados por parte de los desarrolladores de algoritmos de ML. Desde el punto de vista de rendimiento computacional, existen entre sus parámetros de configuración diversas opciones de configuración relativas al grado de paralelismo, que pueden ser fijadas a priori, pero no pueden ser reconfiguradas durante el proceso de entrenamiento o inferencia, por lo que se consideran parámetros rígidos. En situaciones en las que múltiples instancias del framework se ejecutan en una misma máquina, dicha rigidez puede derivar en problemas tales como oversuscription, degradamiento del rendimiento del sistema y/o aplicación e infrautilización de los recursos computacionales. Por lo tanto, resulta importante agregar un grado de elasticidad en Tensorflow, permitiendo aumentar la productividad del sistema en entornos dinámicos multiprogramados. Por otro lado, la utilización de contenedores como método de virtualización ligera permite una mejor administración de los recursos y portabilidad. Existen múltiples planificadores que permiten aprovechar los beneficios de los contenedores, pero solo permiten llevar a cabo una asignación estática de recursos en el momento de su creación, y en algunos casos reasignación de recursos en tiempo de ejecución; en cualquier caso, las aplicaciones en ejecución dentro del contenedor no se encuentran preparadas para reaccionar ante dicho evento, y por tanto no se adaptarán en ningún caso a la modificación en los recursos asignados al contenedor. Por todo lo comentado anteriormente, este trabajo propone el diseño e implementación de un mecanismo completo de elasticidad en el uso de recursos computacionales en el framework Tensorflow, permitiendo la reasignación dinámica de núcleos de cómputo durante la ejecución del algoritmo de ML. Además, se extiende el uso de la elasticidad a contenedores con la implementación de un controlador/cliente que permita administrar los recursos computacionales asignados a los algoritmos de ML que ejecutan internamente. Por último, se implementa un planificador de contenedores elásticos con el fin de gestionar dinámicamente los recursos del sistema entre todos los contenedores activos y definir políticas de planificación que favorezcan el rendimiento global del sistema., Facultad de Informática

There has been a growth of interest in semantic segmentation in recent times, and its employment in tasks such as autonomous driving, medical diagnosis or video surveillance is now crucial. The training and inference processes in Deep Neural Networks (DNNs) are performed in data centres, which causes unbearable latency. Edge Computing is a response to this limitation. Nevertheless, it is restricted by the computing power and energy consumption in devices. This project proposes the implementation of algorithms for semantic segmentation of images using DeepLab and TensorFlow as a basis, along with its adaptation and throughput evaluation in terms of response time in a mobile device among different semantic segmentation models. A Raspberry Pi was used along with a Coral USB Accelerator by Google, which provides an Edge TPU to accelerate inference in Machine Learning by quantizing the models. The final goal is to prove an efficient implementation in this low energy consumption architecture.