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This paper investigates the feasibility of wideband low-noise amplifiers in bipolar silicon-germanium IC technology. Three different design techniques are compared and the most promising one is analyzed in detail and examined on a design example. We propose a design approach based on an LC-ladder structure as the input matching network. Used in combination with the cascode structure amplifier with inductive degeneration, the dual-LC tank employs two resonant tanks so as to achieve wideband input power matching and noise matching simultaneously. Following the design procedure described in the paper, a 20-40 GHz low noise amplifier is designed and the simulation results are provided to verify the proposed approach.

NR 20140805

In this paper a novel outphasing amplification architecture, Transmitted Linear Amplification with Nonlinear Components (T-LINC), is proposed and evaluated. Different from conventional LINC techniques that combine the outphased signals before transmission, the proposed architecture transmits both outphased signals and implements the signal combination in the base-band domain at the receiver side. By digitally combining the signals in the receiver, it is easier to correct gain or phase mismatch existing between the two outphased signals, without adding any extra complexity in the transmitter. Additionally, a power combiner is no longer required in the transmitter. Simulations show that the proposed technique is able to correct transmitter gain and phase imbalance and achieve an ACPR level of -42 dBc and EVM below 2.5 % for 16-QAM signals. Index Terms—Digital combination, digital mismatch correction, linear amplification with nonlinear components (LINC), outphasing amplification, Transmitted LINC (T-LINC). With the recent popularization of nanosatellite technologies, the industry is putting a notable effort into increasing the performance of the systems integrated in these small spacecrafts. In this paper, a novel outphasing amplification architecture to enhance the power efficiency of a satellite downlink is presented and evaluated. Based on a conventional LINC (LInear amplification with Nonlinear Components) architecture, the proposed architecture transmits both outphased signals, and carry out the signal combination in the receiver in the base-band domain. The resulted architecture takes advantage of an efficient signal amplification given by the nonlinear power amplifiers, while the elimination of the signal power combiner from the transmitter, increases the overall power efficiency. We outline and analyze those elements that restrict the performance of this novel approach. The simulations and laboratory experimentation probes the proposed architecture is feasible, and able to improve a ?? % the power efficiency, compared to a classic transmitter front-end architecture.

—By the increased number of antennas and power amplifiers connected to each in 5G system, the linearization methods like Digital Pre-Distortion (DPD) of each power amplifier is inefficient due to antenna imperfections such as crosstalk. Furthermore due to limited area the distance between antennas in array can vary, which leads to unwanted coupling between antennas. A solution to this problem can be treating the amplifiers and antennas as one system and linearizing the main beam signal at receiver rather than on each single power amplifier. In the work described in this paper the whole system including amplifiers, antennas and receiver is treated as a 2-ports system and the impacts of above mentioned constraints are investigated. By increasing the number of antennas and power amplifiers connected to each in 5G system, the linearization methods like digital pre-distortion (DPD) of each power amplifier is inefficient due to antenna imperfections such as crosstalk. As a result of limited area the distance between antennas in array can vary which leads to unwanted coupling between antennas. A solution to this problem could be treating the amplifiers and antennas as one system and linearizing the main beam signal at the receiver rather than on each single power amplifier. In the work described in this paper, the whole system including amplifiers, antennas and the receiver is treated as a 2-ports system and the impacts of the above mentioned constraints are investigated.

Programmable data plane is a key enabler of Software Defined Networking. By making networking devices programmable, novel networking services and functions could be realized by means of software running on these devices. In this paper, we present a lightweight packet processor that could process the packets on the fly as they arrive. As we will see, the area of this packet processor is smaller than a packet parser employing Ternary Content Addressable Memory. As an added benefit, the designed packet processor could also reduce the traffic to the lookup tables on the chip. Moreover, its use is not limited to switches and routers. It could also be used in the Network Interface Cards and offload packet processing tasks. Despite its packet processing capabilities, packet processor instances required for sustaining aggregate throughput of 640 Gbps have area equivalent to the packet parser instances in the Reconfigurable Match Tables Architecture. acceptedVersion

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