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INTRODUCTIONSigns can be placed not only in the construction of a sentence (speech) but also in an abstract linear system, with the difference that in speech, signs are not randomly placed in the order of accompaniment, but that production is said to be affected always from the characteristics of the human subjects (mediators or operators). MATERIALS AND METHODS The effect of mediators on the arrangement of signifiers in the process of speech and texts makes us use multiple and more complex variables in the analysis of signs and discursive systems. The sensory-perceptual mood of the sign user, affected by various phenomena and variables, affects the conditions for the production and reception of signs. These conditions make it necessary to consider different cognitive and emotional categories in analysis. These variables can be represented on the axis of tension and on the square of the discursive systems. RESULTS AND DISCUSSIONThe question is: what is the difference between the production and reception of signs in both normal and abnormal situations (such as rumors) in terms of tension and discursive systems. The most common form of sign production and use can be found in a programmatic and logical discursive system. To the extent that we deviate from the normal situation, the ground is prepared for drawing an accident discursive system. The statement that is produced in the normal state of the signs can be considered equivalent to "news" in the conventional sense, and therefore the opposite point must be interpreted as "false" which, if prevalent, is considered a "rumor". The mechanism of overcoming the situation when "enunciation" can be considered as a rumor in the system of signification is the subject of the present study. The purpose of this article is to explain the mechanism of evolution of signs in the process of discursive evolution in which rumors are produced and transformed. The research hypothesis is that the phenomenon of rumor causes the emergence of an accidental discursive system. In this discursive system, due to the heavy reduction in cognitive categories, the level of tension is at the highest level and the signs are very fluid. In order to examine this situation in a suitable literary text, a text called “The Power of the Rumor” was chosen. This text has been produced and reproduced in various forms, itself as a rumor, in the context of the internet digital space. This text is like a rumor without evidence and has taken a different form in each reproduction. It seemed that this text will better show us the natural mechanism of producing and receiving a signal that carries the concept of rumor. CONCLUSIONThe results show that there is a set of factors that the process of discourse is always influenced by : the energies that affect the linguistic production of the narrator, the scope of vision, the perspective on which the linguistic production is formed, the linguistic challenges that determine the degree of tension in linguistic productions, the image that the narrator has of himself, his partner or discursive rival at all times, constantly changing individual methods or manners of speech that are formed based on cultural and social backgrounds, linguistic capabilities, temporal and spatial conditions, etc., and cognitive, emotional, aesthetic, sensory-perceptual elements. According to research findings, rumors, based on a sensory-perceptual error, in the form of an event, create an accidental discursive system. In the face of such a situation, ordinary people whose actions are more emotionally-reactive, respond in a rejectionist selective approach, but specialist subjects, whose actions are more rational, with an interactive approach, in the form of a communicative respond. There is a causal relationship between the cognitive state and the emotional stress of the actors and their actions and value systems. In this way, the ordinary people, with limited knowledge and under intensive emotional tension, draw an absolute and closed value system, but a specialized subject, with extensive recognition and under low emotional stress, illustrates democratic and open value system. According to the results of this study, accidental discursive system is at the beginning of this process and a programmatic discursive system in its precursor. Ordinary people, due to the lack of cognition and foresight, provide digital logic and strengthen the risky aspect of the system, However, the elites and specialized subjects, based on analog logic, gradually evolve the process of evolution of signs which they direct it till the final goal.According to the research’s results, rumor is a semantic defect produced by the narrator whose physical and sensory-perceptual base is defective (defect, disease) and occurs as an accident. Bringing back the discourse to its ordinary logical situation needs a rational management.

Большое энергопотребление изделий интегральной электроники и дорогостоящие методы их производства, делает масштабирование кремниевых полупроводниковых устройств до размеров менее 50 нм непростой технологической и конструкторской задачей. В последнее время были достигнуты значительные успехи в разработке и исследовании изделий молекулярной электроники: молекулярных проводов, молекулярных диодов, изготовленных из отдельных молекул. Также были получены хорошие результаты в технологии формирования надежного электрического контакта с электропроводящими молекулами. Достижения в области наноэлектроники делают возможным разработку более сложных молекулярных электронных структур, например, цифровых логических схем. В данной работе проведено квантовохимическое моделирование молекулы, выполняющей функцию логического элемента, выполнена оптимизация равновесной пространственной конфигурации молекулы, разработана конструкция и синтезирована топология слоев для изготовления подложки для монтажа молекулы и создания внешних интерфейсов. Полученные результаты демонстрируют перспективность органической электроники как альтернативы кремниевым полупроводниковым материалам при разработке интегральных схем. The high energy consumption of integrated electronics products and expensive methods of their production makes scaling silicon semiconductor devices to sizes less than 50 nm a difficult technological and design task. Recently, significant advances have been made in the development and research of molecular electronics products: molecular wires, molecular diodes made from individual molecules. Good results also obtained in the technology of forming a reliable electrical contact with electrically conductive molecules. Advances in nanoelectronics make it possible to develop more complex molecular electronic structures such as digital logic circuits. In this work, a quantum-chemical simulation of a molecule performing the function of a logical element is carried out, the equilibrium spatial configuration of the molecule is optimized, the design is developed and the topology of the layers for fabricating a substrate for mounting a molecule and creating external interfaces is developed. The obtained results demonstrate the promise of organic electronics as an alternative to silicon semiconductor materials in the development of integrated circuits.

This article introduces the possible usage of the developed programming discourse that can be used to support training in the digital logic area. The discourse merges several programming paradigms into one solution. The intended learners are secondary school students focused on digital system programming. The main intent is to find out whether digital logic curriculum based on Digital Circuits Based Logical Programming (DCBLP) inheritance has positive impact on the students and the way they explore the digital logic itself. Students’ cognitive and affective areas are in the scope of this preliminary research and questionnaires and cognitive tests will help to support the research. Experimental and control groups were used to gather relevant records. To analyse and support the interpretation of the data gathered by questionnaires, the chi-square test (two-tailed) has been used. ANOVA has been used to evaluate data for the achievement test results. The preliminary research revealed there is a possibility of using developed programming discourse DCBLP in digital logic training. Students claim overall usefulness of the discourse in the training, the strong motivation power of the programming discourse itself has not been discovered. From the test we conclude that the performance of the students trained using new programming discourse is significantly better. It is possible to use more different programming paradigms, such as imperative and declarative, in one solution to support training in the area of digital logic. Such solutions can enhance the way the students deal with the programming languages and also supports interdisciplinary relationships.

Molecular programming - a paradigm wherein molecules are engineered to perform computation - shows great potential for applications in nanotechnology, disease diagnostics and smart therapeutics. A key challenge is to identify systematic approaches for compiling abstract models of computation to molecules. Due to their wide applicability, one of the most useful abstractions to realize is neural networks. In prior work, real-valued weights were achieved by individually controlling the concentrations of the corresponding "weight" molecules. However, large-scale preparation of reactants with precise concentrations quickly becomes intractable. Here, we propose to bypass this fundamental problem using Binarized Neural Networks (BNNs), a model that is highly scalable in a molecular setting due to the small number of distinct weight values. We devise a noise-tolerant digital molecular circuit that compactly implements a majority voting operation on binary-valued inputs to compute the neuron output. The network is also rate-independent, meaning the speed at which individual reactions occur does not affect the computation, further increasing robustness to noise. We first demonstrate our design on the MNIST classification task by simulating the system as idealized chemical reactions. Next, we map the reactions to DNA strand displacement cascades, providing simulation results that demonstrate the practical feasibility of our approach. We perform extensive noise tolerance simulations, showing that digital molecular neurons are notably more robust to noise in the concentrations of chemical reactants compared to their analog counterparts. Finally, we provide initial experimental results of a single binarized neuron. Our work suggests a solid framework for building even more complex neural network computation., LIPIcs, Vol. 205, 27th International Conference on DNA Computing and Molecular Programming (DNA 27), pages 1:1-1:20

This dissertation investigates digital transformation, understood here as processes where organizational actors engage in digital innovation and transform their organizations in order to respond to change in their business and technology environments. Specifically, it examines the dynamics of digital transformation, seeking to understand the key sociotechnical elements and their relationships that drive digital transformation processes and influence how they unfold over time. To theorize the dynamics of digital transformation, I synthesize extant knowledge with contributions from four appended research papers. The outset for theorizing in this dissertation is a body of literature that has begun to accumulate knowledge on digital transformation as a distinct phenomenon. Within this literature, I identify three main areas that are vital to understanding digital transformation processes, yet have so far not been sufficiently theorized. First, research on digital transformation often describe it as a complex and longitudinal process that involves several sequences of digital innovation, yet it has primarily been studied in the form of discrete instances of innovation decoupled in time and space. As a result, current knowledge on digital transformation as a longitudinal process is limited. Second, the literature on digital transformation emphasize that interactions between digital business and technology environments and organizations are crucial for explaining why and how digital transformation unfolds. At the same time, however, the literature has so far not been able to offer a conceptualization of these interactions in ways that make formative influence over time visible. Third, existing research on digital transformation has remained dominantly focused on the role of managers and paid limited attention to other organizational actors in digital transformation. Addressing the limitations identified in existing digital transformation research, I draw upon established theoretical concepts and the four appended research papers to theorize a conceptual framework on digital transformation dynamics. The conceptual framework contributes to research by clarifying a set of theoretical concepts and relationships that are instrumental for addressing digital transformation as a sequential and cumulative process, and the actors, agency and actions that realize digital transformation over time. It is supportive of future theorizing of digital transformation as a subject matter related yet distinct from other forms of organizational change enabled by technology use.

Eesti keeles: Antud lõputöö raames loodi kuus praktikumi juhendit “Digitaalsele loogikale”. Varasemad praktikumide juhendid on piirdunud LED-e ja lülitite väljundväärtuste muudmisega. Antud lõputöö raames lisaks eelmainitud sisend-väljund seadmetele lisati ka Pmod lisamoodulite ja nendele vastavate kommunikatsiooni protokollide kasutamise võimalus. Mainitud lisamoodulite praktikumi juhenditesse lisamisega lisandus praktikumide läbijatele parem arusaam tänapäeval kasutusel olevatest sisend-väljund seadmetest ning tõusis ka ülesannete komplekssus aste. Kaks valminud lõputöö juhenditest võeti kasutusse ka 2019. aasta kevadsemestril Tartu Ülikoolis “Digitaalse loogika” praktikumides. Valminud praktikumi juhendi kvaliteedi hindamiseks teostati ka praktikumide läbijate seas küsitlus. Küsitluse tulemuse põhjal võib järeldada, et valminud praktikumi juhend on igati täitnud oma eesmärki ja on praktikumide läbijatele meeldinud. Tagasisidet küsiti ka praktikumijuhendajatelt, kes samuti kiitsid valminud lõputöö selgust, ülesannete keerukust ning uudset lähenemist huvitavate lisamoodulite rakendamisel. In English: Former practical guides of the University of Tartu course “Digital logic” have been limited to using simple IO devices, such as LEDs and switches. This thesis provides six new practical guides to increase the depth of the “Digital logic” course. These new guides add the option of using Pmod modules to provide students a better understanding of modern IO devices and communication protocols. Two of the provided guides were taught in the spring semester of 2019 in the University of Tartu course “Digital logic”. Feedback was asked of the students to measure the quality of the guides. Based on the results it can be concluded that the guides fulfilled their objectives and were liked by the students. Feedback was also asked from the practical instructors of the course and they approved of the difficulty and the new approach of these guides.

The paper describes the adaptation of the Computer Architecture laboratory works given at the Faculty of Engineering in Foreign Languages from the University POLITEHNICA of Bucharest to the new trends in digital logic design. The laboratories are given in a gradual approach, starting with simulation, continuing with breadboard design and finishing with circuits made on perf-board. We are preparing now to complement the practical side of the laboratory with Field-Programmable Gate Array (FPGA) design, where the students will conceive, simulate, synthesize and implement the circuits already studied in the initial approach that used simulation followed by integrated circuits practical design.

Bu tezde, bir Yüksek-Seviyeli Sentez (HLS) aracı kullanarak gerçek zamanlı bir görüntü birleştirme algoritmasının uygulaması sunulmuştur. Görüntü birlerştirme bir veya birden fazla görüntüyü bir renk dönüştürme yöntemi kullanarak birleştirir. Farklı uygulamalar için saniyedeki kare sayısı (fps) ve/veya çözünürlük gereksinimi farklı olabilir. Görüntü işleme algoritmasının özellikleri sıkça değişebileceğinden yeni tasarım yapmak gerekebilir. Hedef platform Sahada Programlanabilir Kapı Dizisi (FPGA) olduğunda genellikle hızlı hatta optimize edilmiş donanım gerçeklemesi gereklidir. Bütün bu gereksinimler, sadece HLS aracı ile karşılanamaz. Alışılmışın dışında boru hattı yöntemleri, Yazmaç Transfer Seviyesi (RTL) kodlama yerine RTL üreten araç kodlama ve mantık/yazılım arayüz bağlantısını yapmanın yaratıcı yolları, yukarıda belirtilen gereksinimleri karşılamamıza izin verir. Bütün bu yaklaşımlarla beraber, görüntü birleştirme algoritmasının 3 farklı versiyonunu (farklı fps ve/veya çözünürlükte) Intel Altera Cyclone IV ve Arria 10 FPGA üzerinde oldukça kısa zamanda çalıştırdık. Görüntü birleştirme algoritmasında standart sapma hesaplaması bulunmaktadır, gerçeklemesi her görüntü karesindeki tüm piksel değerlerinin toplanmasını gerektirir. Bu nedenle, Alan-Verimli İndirgeme Devresi (AERC) ve Hız-Alan Verimli İndirgeme Devresi (HSAERC) diye adlandırılan iki özgün indirgeme devresi (ve dolayısıyla RTL üreteçleri) tasarladık. Kendi Verilog RTL kod üreteçlerimizi kullanarak birçok indirgeme devreleri (AERC ve HSAERC) ürettik. AERC ve HSAERC devreleri, Xilinx Virtex-II Pro ve Virtex-5 FPGA'leri üzerinde gerçeklenmiştir ve sentez sonuçları literatürdeki en gelişmiş tasarımlarla karşılaştırıldı. AERC tasarımı alan kullanımı bakımından literatürdeki tasarımlara göre daha iyidir. Diğer yandan HSAERC tasarımı ise performans bakımından diğer tasarımlardan üstündür. In this thesis, the hardware implementation of a real-time image fusion algorithm using a High-Level Synthesis (HLS) tool is presented. Image fusion combines two or more images through a color transformation process. Different applications may require different frames per second (fps) and/or resolution. Yet the specifics of the image-processing algorithm may frequently change causing redesign. If the target platform is Field Programmable Gate Array (FPGA), usually rapid yet optimized hardware implementation is required. All these requirements cannot be met only by HLS. Clever approaches in terms of architectural techniques such as unorthodox ways of pipelining, coding Register Transfer Level (RTL) generators instead of RTL, and creative ways of porting interface logic/software allowed us to meet the requirements outlined above. With all these in our arsenal, we were able to get 3 versions of the image fusion algorithm (with different fps and/or resolution) running on Intel Altera Cyclone IV and Arria 10 FPGAs in a fairly short amount of time. In the image fusion algorithm, there is a standard deviation calculation, implementation of which requires accumulation of all pixel values of each frame. Hence, we designed two novel pipelined reduction circuits (and hence their RTL generators) that are named Area- Efficient Reduction Circuit (AERC) and High-Speed Area-Efficient Reduction Circuit (HSAERC). We generated several reduction circuits (AERC and HSAERC) using our own Verilog RTL generators. AERC and HSAERC designs were implemented on both Xilinx Virtex-II Pro and Virtex-5 FPGAs, and their synthesis results were compared with state-of-the-art designs in the literature. AERC design is better than the existing designs in the literature in terms of area utilization. On the other hand, HSAERC design is better than other designs in terms of performance. 61

Squared weight is an excellent metric on which to base codeword selection in DC-free multimode coding. It has, however, been considered too complex to implement in practice. In this Letter, the authors present a simple approach to evaluate this metric that enables it to be implemented in high-speed digital logic.

Boru hattı konsepti saat frekansını yükselten ve kaynak kullanımını azaltan temel bir sayısal donanım tasarımı tekniğidir. Boru hatlı aritmetik modülleri kullanan bir boru hatlı Sahada Programlanabilir Kapı Dizileri (FPGA) modülünün tasarlanması, özellikle Başlatma Aralığı birden fazla olduğunda, tahsisat, çizelgeleme ve bağlama konularında zorlu bir geliştirme sürecine sebep oluyor. Yüksek işlem yüküne sahip algoritmalar söz konusu olduğunda, örneğin video işlemede, bu hata yapmaya eğilimli ve zaman alan süreçleri otomatikleştirmek son derece gereklidir. Bu tezde, FPGA'de bir optik akış tasarımının hızlı geliştirilmesi sırasında yaşadığımız Yüksek Düzeyli Sentez (HLS) deneyimimizi paylaştık. Elimizdeki optik akış tasarımı ve benzeri görüntü işleme problemleri için geliştirdiğimiz HLS aracını ve Vivado HLS'yi kullanarak ayrı ayrı aynı tasarımı gerçekleştirdik. Bu tez, sahip olduğumuz tasarım problemini açıklıyor ve daha sonra kendi HLS aracımızı detaylı bir şekilde anlatıyor. Geliştirdiğimiz araç, döngüsel ara iterasyon bağımlılıklarını işleyememe dışında oldukça genel amaçlı bir araçtır. Ayrıca, `boruhatlı çoklayıcılar` gibi HLS'ye yeni kavramlar getiriyor. Sentez sonuçları, Vivado HLS'ye kıyasla daha iyi zamanlama veya daha iyi alan sonuçları elde edebildiğimizi gösteriyor. Dahası, HLS aracımızın Verilog RTL'si Vivado HLS'den daha okunabilirdir. Uniteler ve yazmaçlar için üretilen kaynak zaman tabloları da düşünüldüğünde, tasarımcının RTL'de hata ayıklamasını ve elle değişiklik yapabilmesini daha kolay hale gelmektedir. Pipelining concept is a fundamental technique in digital hardware design, which maximizes the clock frequency or minimizes the resources. Designing a pipelined Field Programmable Gate Array (FPGA) module using pipelined arithmetic modules brings us challenging allocation, scheduling, and binding issues, especially when the Initiation Interval is more than one. In the case of algorithms with high computational cost, for ex., in video processing, we need to automate these error prone and time consuming processes. In this thesis, we share our experience in using High-Level Synthesis (HLS) for rapid development of an optical flow design on FPGA. We have performed HLS using Vivado HLS as well as a HLS tool we have developed for the optical flow design at hand and similar video processing problems. The thesis describes the design problem we have and then discusses our own HLS tool. The tool we developed is general-purpose except for the inability to handle cyclic inter-iteration dependencies. It also introduces novel concepts to HLS, such as pipelined multiplexers. The synthesis results show that we can achieve better timing or better area results compared to Vivado HLS. Furthermore, the Verilog RTL our HLS tool outputs is better than Vivado HLS in terms of readability. Also, the time-resource tables we produce for both arithmetic units and registers make it easier for the designer to debug and modify the RTL. 65

Submitted by Boris Flegr (boris@uerj.br) on 2021-01-06T19:13:36Z No. of bitstreams: 1 Marcelo dos Reis Farias.pdf: 3319101 bytes, checksum: 569ff3e1f509186ab46fcfd00cd7d8d0 (MD5) Made available in DSpace on 2021-01-06T19:13:36Z (GMT). No. of bitstreams: 1 Marcelo dos Reis Farias.pdf: 3319101 bytes, checksum: 569ff3e1f509186ab46fcfd00cd7d8d0 (MD5) Previous issue date: 2016-10-31 In popular terms, it has been said that the machines speak and through sounds and vibration we can hear their complaints and diagnose their diseases . The condition monitoring of rotating machines by measuring and vibration analysis is the process in which a machine is periodically evaluated by measuring and analyzing its condition by means of vibration signals. This procedure can be carried out at three levels: 1-Overall measurement of vibration levels, to know the severity of vibration and compare with preset limits; 2- Frequency and time dominium spectrum analysis to detect where the defects come from; 3- Special techniques that can better detail the level, location and type of a defect or a malfunction. This study aims to evaluate some of these special techniques such as Full Spectrum, SPM spectrum, Órbita, phase analysis / ODS and Envelope. These techniques were applied on an experimental rig by imposing various defects in these mechanisms such as misalignment, imbalance, gear defects, problems in bearings, etc. and measuring its vibration response. The results obtained by each technique were evaluated and compared. The final analysis is made using the method of digital logic by creating tables of comparative techniques for each type of defect. Doing so, it way possible to identify which technique is best to diagnose a particular type of defect. Em termos populares, tem sido dito que: as máquinas falam e através dos seus sons e vibração podemos ouvir suas queixas e diagnosticar suas doenças . O monitoramento da condição de máquinas rotativas através da medição e análise de vibração é o processo no qual uma máquina é avaliada periodicamente através da medição e análise de vibração e suas condições são verificadas através dos sinais de vibração. Este monitoramento pode ser realizado em três níveis: 1- Medição global dos níveis de vibração, para conhecer a severidade da vibração e comparar com limites pré-estabelecidos; 2- Análise do espectro de frequência, para detectar de onde vem a vibração e possíveis defeitos; 3- Técnicas especiais, que podem detalhar melhor o nível, local e tipo do defeito ou mal funcionamento. Este trabalho tem o objetivo de avaliar algumas dessas técnicas especiais como: Full Spectrum, SPM spectrum, Órbita, Análise de fase / ODS e Envelope. Estas técnicas foram aplicadas numa bancada experimental que permite introduzir diversos defeitos nos mecanismos presentes como: desalinhamento, desbalanceamento, defeitos em engrenagens, problemas em rolamentos, etc. Os resultados obtidos através de cada técnica foram avaliados e comparados. A análise final dos resultados é expressa utilizando o método da lógica digital para criação de tabelas comparativas das técnicas para cada tipo de defeito, sendo possível identificar qual técnica é melhor para diagnosticar um tipo específico de defeito.

El presente artículo se basa en el trabajo de investigación realizado para optar a la categoría de Profesora Asistente de la Cátedra de Relaciones Públicas de la Escuela de Comunicación Social de la Universidad Central de Venezuela. Su propósito es contribuir con la comprensión de las implicaciones de la lógica digital en la comunicación de las organizaciones contemporáneas, y colaborar epistemológicamente con la proyección del sentido de la profesión del comunicador. Para este estudio se definió a la lógica digital como el ordenamiento dinámico, que resulta de la interacción del usuario, las técnicas, las prácticas, las actitudes y valores que se desarrollan a la par del ciberespacio. El hallazgo principal, es que la lógica digital es un modelo útil para caracterizar las mutaciones comunicacionales contemporáneas, pues ayuda a describir un escenario donde la simetría comunicacional reina y las estructuras de redes, invitan a un renacer del protagonismo del sujeto. Es el carácter autoorganizado de la plataforma digital el que impulsa la emergencia de nuevos principios organizadores, como la inteligencia de colaboración y el orden meritocrático centrado en la pertinencia de contenidos. This paper is based on the research prior to my applying for the post of Assistant Professor in the Public Relations Department of the Social Communication School at the Universidad Central de Venezuela. Its aim is to contribute to the understanding of the digital logic implications in the contemporary organizations´ communications, and to collaborate, from an epistemic point of view, with its projected meaning in the communications area. In this sense, digital logic is defined as the dynamic organization resulting from user interaction, technology, practices, attitudes and values that develop at the same pace as the cyberspace. The main finding was that digital logic is a valuable model to characterize current communicational mutations, because it helps describe a scenario, where communicational bidirectionality prevails, and the network structure empowers the rebirth of self-protagonism. It is the self-organized feature from the digital platform, which encourages new organizing principles like collaborative intelligence and meritocratic order, centered on content relevance.

In order to use a smart phone or smart watch with the near field communication (NFC) standard to read sensor data from a micro-implant, an NFC tag with integrated ADC and sensor front-end is implemented. An NFC digital protocol module is combined with an energy efficient front-end, ADC, energy harvester and NFC data link to form a passive NFC tag with a fully integrated and complete sensor interface. This work builds on previous work where parts of this system have been designed and tested as standalone solutions. Previously, a sensor interface ASIC has been developed that provides the front-end to a resistive or capacitive sensor and converts its output (e.g. blood sugar concentration) into digital data ready to be transferred. Another NFC physical layer ASIC has been developed which hosts the energy harvesting and physical communication layer required to operate with an NFC enabled mobile phone, or other NFC readers. An implementation of the NFC digital protocol has been created and tested on a FPGA together with the physical communication layer and front-end and ADC. The FPGA implementation was modified further to be synthesized and combined with the two previous ASICs into a single ASIC. A power-on reset circuit was implemented for the digital core’s startup conditioning on power up. The main contributions of this work has been to add the higher level NFC protocol control logic module as well as a power-on reset circuit, and to integrate all of these modules onto a single system-on-chip (SoC).

Sve veća zastupljenost tehnologije sa ekranom na dodir otvorila je nove mogućnosti po pitanju interakcije čovjeka i računala. U tom duhu došlo se na ideju razvoja mobilnog klijenta za uređivanje logičkih shema. Shema treba biti neovisna o dimenzijama ekrana i treba ju moći simulirati. Kao riješenja prethodnih zahtjeva, razvijena je Android aplikacija koja omogućava skaliranje, pomicanje i simuliranje uređenih grafičkih prikaza. Aplikacija pametno raspolaže ograničenim prostorom na ekranu ako je riječ o mobitelima i ostvaruje interkaciju korisnika i računala pomoću standardnih gesti za uređaje sa ekranima na dodir. The extensive use of technology with touchscreen opened up new possibilities in terms of human-computer interaction. In this spirit, there was an idea of developing a mobile client for editing logic schemes. The scheme should be independent of the size of the screen and should be able to be simulated. As a solution of the preceding claims an Android application was developed that allows scaling, moving and simulating landscaped graphics. Application wisely uses its space on the screen when it comes to the cell phones and realizes the human-computer interaction using standard gestures for devices with touch screens.

Procesom automatizacije nastoji se provesti upravljanje procesima bez izravnog utjecaja čovjeka. Upravljanje je najjednostavniji oblik automatizacije te omogućava mijenjanje izlaza promjenom ulaznih signala. Koristi se većinom programsko upravljanje gdje mikrokontroleri električnim signalima izazivaju promjene izlaza. Veliki broj izlaznih sklopova kojima treba upravljati predstavlja problem zbog ograničenja broja signala koje mikrokontroler može dati. Ovaj rad daje jednostavan algoritam kojim se omogućuje upravljanje većeg broja releja pomoću mikrokontrolera. U konačnici algoritam je izveden u obliku tiskane pločice. Automation is way of controlling processes without direct human intervention. Control is the simplest way of automation which allows output variability just by changing inputs. In the industry we use microcontrollers to give input signals. Problem is in large number of outputs that we need to change with limited number of inputs. This paper gives simple algorithm for relay control with microcontroller outputs. In the end algorithm is applied on PCB.

Computers are becoming indispensable for manipulating most everyday consumer products, ranging from c ommunications and domestic electronics to industrial processes monitoring and control. High performance computer design is not only subject to the technology used for its implementation, it is also a matter of efficient training. The skills that must preva il in a good computer designer c o me from the type of courses taken and the tools employed during them. This work shows the design of an 8 - bit RISC soft - core processor dedicated to a complete understanding of computer architecture. We consider this Processo r an effective hands - on training solution for the comprehension of a computer from its lowest level up to testing.

Fluid handling procedures like serial dilution are common to a number of laboratory protocols. Such procedures are time consuming and require laboratory training to be performed. Thus using microfluidics technology for such procedures is very promising. Whereas there are a number of innovative lab-on-a-chip systems that use microfluidics to miniaturize lab procedures, these devices require heavy off-chip equipments to operate. For example a typical setup consists of a pump, a computer, tons of tubing and more. Such dependency on off-chip machinery limits microfluidic liquid handling devices only to highly-equipped settings. Therefore to exploit the microfluidic technology such that the devices are also useful for limited resource settings and other applications (e.g. point-of-care diagnostics), it is important to minimize or eliminate the dependence of these devices on off-chip control equipments. Automation of fluid-handling microfluidic devices can be achieved by incorporating the control logic in the chip design. Pneumatic digital logic structures can be built on the chip and can be used to provide timing reference and also control signals for operations such as mixing/diluting, selection, storage and routing of liquid on the chip. This project explores the usefulness of pneumatic digital logic for the purpose of automation of fluid handling microdevices. Serial dilution, which is a very common laboratory procedure, is automated on-chip such that the chip requires only one constant vacuum source for power and one clock signal to operate. Logic circuits such as the microfluidic oscillator, the finite state machine and, decoding circuits are employed to automate a fluid-handling circuit on the chip. This report discusses how these pneumatic digital logic structures can be integrated and optimized in order to control and operate a fluid-handling structure that carries out on-chip serial dilution.

It's been quite a while since scientists are seeking for the ancestor of von Neumann computing architecture. Among the most promising candidates, memristor demonstrates advantageous characteristics, which open new pathways for the exploration of advanced computing paradigms. In this work we propose the design of a novel crossbar geometry, which is heterogeneous in terms of its cross-point devices, allowing for the realization of true in-memory digital logic computations. More specifically, it is a combination of two stacked crossbar arrays with a shared intermediate nanowire layer. The variety of available cross-points types allows the execution of parallel memristive logic computations, where the logic state variable is voltage. Moreover, the utilization of insulating patterns in the crossbar arrays, at the expense of a small area-overhead, permits the simultaneous parallel read/write memory operation of two memory words. Memory/logic operation is determined through control signals driven from the peripheral CMOS-based driving circuitry, which also comprises row/column decoders, tri-state drivers, and summing/ sense amplifiers to allow for the proper programming/reading of the memristive cross-points

In this paper we describe an integrated platform for teaching and learning of Digital logic. The developed platform is based on web technologies. It helps teachers to prepare learning and assessment materials and to track student progress. It allows students to communicate with teaching staff, to complete laboratory exercises, to learn and to practice using self-assessment interactive problems, all at their own pace and time. We investigated how students perceived several aspects of this platform using anonymous poll. The obtained results are presented and discussed.

Chips was devoted to exploring whether the wealth of existing fault-tolerant distributed algorithms research can be utilized for meeting the challenges of future-generation VLSI chips. Participants from both the distributed fault-tolerant algorithms community, interested in this emerging application domain, and from the VLSI systems-on-chip and digital design community, interested in well-founded system-level approaches to fault-tolerance, surveyed the current state-of-the-art and tried to identify possibilities to work together. The seminar clearly achieved its purpose: It became apparent that most existing research in Distributed Algorithms is too heavy-weight for being immediately applied in the ���core��� VLSI design context, where power, area etc. are scarce resources. At the same time, however, it was recognized that emerging trends like large multicore chips and increasingly critical applications create new and promising application domains for fault-tolerant distributed algorithms. We are convinced that the very fruitful cross-community interactions that took place during the Dagstuhl seminar will contribute to new research activities in those areas.

From September the $7^{\text{th}}$, 2008 to September the $10^{\text{th}}$, 2008 the Dagstuhl Seminar 08371 ``Fault-Tolerant Distributed Algorithms on VLSI Chips '' was held in Schloss Dagstuhl~--~Leibniz Center for Informatics. The seminar was devoted to exploring whether the wealth of existing fault-tolerant distributed algorithms research can be utilized for meeting the challenges of future-generation VLSI chips. During the seminar, several participants from both the VLSI and distributed algorithms' discipline, presented their current research, and ongoing work and possibilities for collaboration were discussed. Abstracts of the presentations given during the seminar as well as abstracts of seminar results and ideas are put together in this paper. The first section describes the seminar topics and goals in general. Links to extended abstracts or full papers are provided, if available.

A 64b inductively coupled organic RFID tag on foil is demonstrated at 13.56MHz. The digital logic foil comprises 414 pentacene transistors and is powered by a pentacene double half-wave rectifier, connected to an inductive antenna. The data rate is 787b/s with load modulation behind the rectifier (DC). Also shown is a functional AC-modulated organic RFID tag. ©2008 IEEE. ispartof: pages:290-291 ispartof: Proceedings of the IEEE International Solid-State Circuits Conference - ISSCC vol:51 pages:290-291 ispartof: IEEE International Solid-State Circuits Conference - ISSCC location:San Francisco, CA USA date:3 Feb - 3 Feb 2008 status: published

A 64b inductively coupled organic RFID tag on foil is demonstrated at 13.56MHz. The digital logic foil comprises 414 pentacene transistors and is powered by a pentacene double half-wave rectifier, connected to an inductive antenna. The data rate is 787b/s with load modulation behind the rectifier (DC). Also shown is a functional AC-modulated organic RFID tag. ©2008 IEEE.

Ill ÖZET Yüksek Lisans Tezi SAYISAL MANTIK DEVRELERİNİN BİLGİSAYARDA BENZETİMİ Bu tezin konusu, sayısal mantık devrelerinin bilgisayarda modellenmesi ve bütün mümkün şartlar altındaki davranışlarının incelenmesi ile ilgili PASCAL Programlama Dilinde genel amaçlı bir yazılımın tasarlanıp gerçekleştirilmesidir. Bu benzetim programında AND, NAND, OR, NOR, EXOR, EXNOR ve NOT Kapıları, JK, D, T ve RS Flip-Flopları, Yarım Toplayıcı (H.A), Tam Toplayıcı (F.A), l*2'lik Kod Çözücü (Decoder), 2*4'lük Kod Çözücü, 2*1' lik Kodlayıcı (Encoder), 4*2' lik Kodlayıcı, 2*1' lik Bilgi Seçici (MUX), 4*1' lik Bilgi Seçici, 1*2' lik Bilgi Dağıtıcı (DEMUX), 1*4' lük Bilgi Dağıtıcı, 2 bit' lik Kaydedici (Register), 4 bit' lik Kaydedici gibi devre elemanlarının benzetimi kullanılabilmektedir. Herhangi bir devre elemanının yerleştirilmesi, iptal edilmesi veya yerinin değiştirilmesi, devre elemanları arasına hatların döşenmesi veya iptal edilmesi, devre elemanlarının girişlerine girdilerin yerleştirilmesi veya iptal edilmesi, herhangi bir devre elemanının herhangi bir çıkışı üzerindeki çıktının hesaplanması, ekrandaki devrenin sağa, sola, yukarı, aşağı kaydırılması, çizilen bir devrenin kaydedilmesi veya kaydedilmiş herhangi bir devrenin geri çağırılması gibi işlemler fare (mouse) ve klavye (keyboard) yardımıyla kolayca yapılmaktadır. i-royıamın gerçekleştirilmesinde 30*20' lik bir A matrisi kullanılmıştır. PUT Altprogramı bu matristeki sayısal değerleri kullanarak devrenin şeklini çizer. Devrenin her değişmesi matrisin değişmesi demektir. Bu yüzden matrisin her değişmesinde PUT Altprogramı tekrar çalışarak önceki devre şeklini silip yeni devre şeklini çizer. Anahtar Kelimeler: Benzetim, Sayısal Mantık Devreleri, Yazılım, Tasarım. IV SUMMARY M. Sc. Thesis COMPUTER SIMULATION OF DIGITAL LOGIC CIRCUITS The main purpose of this thesis is to design and implement a general-purpose software which is related in modelling of digital logic circuits on computer screen and examine the behavior of them at any possible conditions by using PASCAL programming language. In this simulation program, simulation of the circuit elements such as AND, NAND, OR, NOR, EXOR, EXNOR and NOT gates, JK, D, T and RS Flip-Flops, Half Adder, Full Adder, 1*2 Decoder, 2*4 Decoder, 2*1 Encoder, 4*2 Encoder, 2*1 Multiplexer, 4*1 Multiplexer, 1*2 Demultiplexer, 1*4 Demultiplexer, 2 bit Register, 4 bit Register can be used. To put or cancel any circuit element, to move any circuit element from one place to another, to put or cancel the wires among the circuit elements, to put or cancel inputs to the inputs of the circuit elements, to find the output on any output of any citcuit element, to move to the circuit in the screen to the right, left, up or down to register any circuit was drawn or to recall any circuit was registered are easily done by means of a mouse or a keyboard. Out in the implementation of the program, an A (20*20) matrix is used. The subroutine PUT draws the shape of the circuit by using numerical values from this matrix. Every change of the circuit means a change of the matrix. Therefore, by execution of the subroutine PUT, for any change of the matrix, the subroutine PUT is reexecuted to delete the preceding circuit and draw the new shape of the circuit. Keywords: Simulation, Digital Logic Circuits, Software, Design. 37

ÖZET Bu çalışmanın birinci bölümünde Dijital lojik kaplarına ilişkin temel tanımlar verilmiştir. İkinci bölümde Ardaşık (combinatonal) dijital lojik devreler ve ardaşık (sequential) olmayan dijital lojik devreleri matematiksel olarak en genel şekilde tanımlanmıştır. Üçüncü bölümde, FIip-FIop kavramını matematiksel olarak tanımladıktan sonra Flip-Flop'ların özellikleri incelenmiştir. Son bölümde, önceki bölümlerde verilen bilgilerin aracılığı ile ardaşık devre ve sayaç tasarımı yapılmıştır. 39 SUMMARY In the first section, definition of digital logic gates have been given. In the second section, the Combinational digital logic circuits and the sequential digital logic circuits have been defined with mathematical notations. In the thirth section, after the Flip-Flops definition have been given, the pecularity of the Flip-Flops have been examined. In the last section, the combinational digital logic circuits and the counter design have been carried out by the means of given knowledge in the previous chapter. 40 42

YÖK/DB Endüstriyel Eğitim Projesi kapsamındaki meslek yüksek okul larında okutulmakta olan Dijital Lojik dersi için bir Model Öğretim Rehberi oluşturmak üzere bu çalışma gerçekleştirilmiştir. Bu amaçla YÖK/DB Tekniker Eğitimi Projesi çerçevesinde bir danış manlık ve öğretim kadrosu tarafından hazırlanmış bu dersin öğreti- mininin genel hatlarını veren bir çalışma, birinci ve ikinci bölüm de verilmiştir. Bu kısımda hiç bir düzeltme yapılmadan YÖK/DB tara fından düzenlendiği şekliyle aktarılmıştır. Üçüncü bölümde; YÖK/DB 'nın belirlediği öğretim programı çerçeve sinde dersin en verimli bir şekilde verilebilmesi için dönemi ik çalışma gerçekleştirilmiştir. Dördüncü bölümde ise daha da detaya inilerek haftalık örnek ça lışma verilmiştir. Beşinci bölümde de Dijital Lojik dersinin bir haftalık bölümü, teo rik bilginin nasıl verileceği; dersane, laboratuar esnasında ve ev de çalışma sözkonusu olduğu zaman süre kullanımı derinlemesine ir delenmiş ve `ÖRNEK EĞİTİM MODÜLÜ` gerçekleştirilmiştir. Altıncı bölümde ise çalışma ile ilgili bir yorum yapılarak öneriler sıralanmaktadır. n This project is a `MODEL TEACHING GUIDE` for the curriculum of Digital Logic Classes studied in the YÖK / World Bank Industrial Project. In the first and second chapter; YÖK / World Bank Technician Training Project Tekniker curriculum is given. [1] In the third chapter; scheme of the first semester work is given for the curriculum of Digital Logic Classes studied in the YÖK / World Bank Industrial Project. In the fourth chapter; a detailed weekly teaching work can be seen for Digital Logic Classes. In the fifth chapter; the more detailed work is given for one unit. This unit is the 11 th unit which is named `Latches and R-S Flip- Flop Circuits`. This work contains of the theorical part of the unit, laborotory applications and how to use the time more accurate. In the last chapter; the final comment is made about this project and the recommendations are given. In the additional part; some books' contents and the references can be seen. m 128

The development of a multi-channel interior communication system utilizing a single wire as a transmission line was undertaken in this paper. The principle of time multiplexing was used incorporating the Pulse Amplitude scheme of modulation. Synchronization was accomplished by continuously transmitting a synchronization pulse from one "Master" station to all other "Slave" stations. This system permits mutually exclusive conversations between any stations concurrently. A master station and one slave station were built and tested. Using a 10-kHz sampling frequency, a frequency response of from 100 Hz to 4.8 kHz was obtained. By using solid-state devices throughout, the size and weight of each station are minimized. This in conjunction with the need for only one connecting wire, make this system ideal for modern aircraft. http://archive.org/details/amultichannelint1094512697 Lieutenant, United States Navy Approved for public release; distribution is unlimited.