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Systematic review.We aimed to provide a comprehensive overview of the English and Chinese literature reporting epidemiological data on spinal cord injury (SCI) in China.3 English and 3 Chinese language electronic databases were searched from the earliest record to 15 March 2020. Sociodemographic characteristics, incidence rates, etiology and lesion characteristics, in-hospital mortality, and secondary health conditions and complications were extracted from included reports.A total of 51 studies were included, 32 in the Chinese language. Forty-seven studies were based on hospital records. Mean age of incident cases ranged from 34 to 55 years and male-to-female ratios ranged from 0.35:1 to 15.3:1. SCI incidence varied from 14.6 to 60.6 per million. Thirty-five studies reported only on traumatic SCI with traffic accidents, high falls, low falls and being hit by objects being the most common causes. Specific causes for non-traumatic SCI were poorly reported. Proportions with tetraplegia and complete injury ranged from 37.4% to 82.0% and 14.1% to 73.9%, respectively. Reported in-hospital mortality attributed to SCI varied from 1.1% to 18.4%. Leading cause of in-hospital mortality for acute SCI was respiratory problems; respiratory problems, urinary tract infections and pressure sores were the most common complications.Epidemiological data on SCI in China are only available for a limited number of provinces and mostly outdated. Updated data on incidence with accurate geographical information and etiology across all Chinese provinces are needed for targeted implementation of preventive strategies. Research on community outcomes needs to be developed in China.

The material loss caused by bubble collapse during the micro-nano bubbles auxiliary chemical mechanical polishing (CMP) process cannot be ignored. In this study, the material removal mechanism of cavitation in the polishing process was investigated in detail. Based on the mixed lubrication or thin film lubrication, bubble—wafer plastic deformation, spherical indentation theory, Johnson—Cook (J—C) constitutive model, and the assumption of periodic distribution of pad asperities, a new model suitable for micro-nano bubble auxiliary material removal in CMP was developed. The model integrates many parameters, including the reactant concentration, wafer hardness, polishing pad roughness, strain hardening, strain rate, micro-jet radius, and bubble radius. The model reflects the influence of active bubbles on material removal. A new and simple chemical reaction method was used to form a controllable number of micro-nano bubbles during the polishing process to assist in polishing silicon oxide wafers. The experimental results show that micro-nano bubbles can greatly increase the material removal rate (MRR) by about 400% and result in a lower surface roughness of 0.17 nm. The experimental results are consistent with the established model. In the process of verifying the model, a better understanding of the material removal mechanism involved in micro-nano bubbles in CMP was obtained.

In the flexible stretch bending of multi-point roller dies process, the deformation of workpiece is mainly driven by clamps. Therefore, the movement track of clamp has a great influence on the forming effect of workpiece. Y-profile, T-profile, and L-profile are taken as the research objects. Simulation and experiments are carried out with two different movement tracks. The influence of the movement tracks on shape error, springback error, and thickness variation of different profiles is discussed. The experimental results of the three profiles processed by the double-sided forming method are consistent with the simulation results, which proves the accuracy of the numerical simulation. The results show that the movement track has a great influence on shape error. Compared with double-sided forming, one-sided forming can effectively reduce springback error. The two different movement tracks have no obvious influence on thickness change.

An innovative method of digestive tract reconstruction following proximal gastrectomy, the uncut interposed jejunum pouch, esophagus and residual stomach double anastomosis(Uncut-D), was established in recent years. In order to fully clarify the superiority of the procedure, this study has conducted a systematic analysis and thorough discussion.118 patients with adenocarcinoma of the esophagogastric junction who underwent proximal gastrectomy were enrolled in this study. According to the methods of digestive tract reconstruction, these patients were divided into three groups: Uncut-D(n = 43), esophagogastrostomy (EG, n = 36), jejunal interposition (JI, n = 39).The preoperative indicators, surgical complications and related indicators of postoperative quality of life were analyzed.There were no significant differences in preoperative data among all groups (P 0.05); The digestive tract reconstruction time in Uncut-D group was more than that in EG group, and less than that in JI group (P 0.05). The incidence of esophageal anastomotic stenosis in Uncut-D group was significantly lower than that in EG group (P 0.05); In Uncut-D group, the incidence of reflux esophagitis, postoperative nutrition index(PNI), weight recovery and Visick classification were significantly better than those in EG group (P 0.05), furthermore, the incidence of delayed gastric emptying,PNI and weight recovery were better than those in JI group (P 0.05).The Uncut-D procedure gave full play to jejunal continuity and the advantages of pouch, and played a valuable role in gastric and cardiac replacement, which significantly reduced long-term complications, improved postoperative nutritional status of patients and long-term quality of life.

Flexible stretch-bending of multi-point roller dies technology is a new three-dimensional forming technology for profiles. Compared with the traditional stretch-bending process, the three-dimensional deformation of the profile can be formed at one time, and the cost of the die is greatly reduced and the production efficiency is improved. The die is an important component of flexible stretch-bending of multi-point roller dies equipment. Discrete die is the focus of this paper. The finite element model of flexible stretch-bending of multi-point roller dies is established. Taking T-profile and L-profile as research objects, the effect of die arrangement on strain, shape error, thickness distribution, and springback error is studied. The non-contact area between profile and die is one of the important factors that affect the 3D deformation of profile. By comparing the numerical simulation results with the experimental results, the effect of the non-contact area length on the three-dimensional deformation of profile is analyzed. The results show that with the increase of the non-contact area length, the shape error of profile increases, the thickness of profile web becomes thinner more seriously, and the springback error of profile increases after unloading.

Springback compensation is considered as the best method to reduce springback error. In view of the springback defect of 3D deformed workpiece, a springback compensation method based on variable compensation factor is proposed. This method can accelerate the convergence speed of iterative compensation. In this paper, the 3D flexible stretch bending of multi-point roller die technology (3D FSB-MPRD) is introduced firstly, and then, the principle of the springback compensation method based on variable compensation factor is explained. In order to improve the springback compensation accuracy of workpiece, the total springback compensation process is divided into horizontal bending springback compensation and vertical bending springback compensation. Taking the T-shaped profile with variable curvature as the research object, the die surface is optimized and the optimal springback compensation factor is obtained by using numerical simulation after multiple iterations. Finally, the results of springback compensation are compared with the desired shape. And the effectiveness of the springback compensation method based on variable compensation factor is verified by comparing the simulation results with the test results.

With the increasing demand of the parts with multi-segment curvature, long length, and complex section shape, the required target shape is more and more difficult to meet. In this article, a flexible three-dimensional (3D) multi-point stretch bending processing method for a roller die is proposed, and a flexible 3D stretch bending equipment of a roller die is developed. With the application of flexible 3D stretch bending technology of roller dies, the complex 3D parts can be formed at one time with only two degrees of freedom. In order to better evaluate the springback deformation of 3D parts, the total springback process of the flexible 3D stretch bending parts of a roller die is divided into two parts: horizontal bending springback distance and vertical bending springback distance. The springback law of different length profiles is studied by numerical simulation and compared with the experiment. From the perspective of springback, this study analyzes the parts produced by the 3D FSBRD process and studies the influence of different process parameters on springback.

Resistive random access memory device (RRAM) has been widely used in various novel circuit systems, such as memory, artificial intelligence, and neural networks, due to its unique memory characteristics. However, there are very few studies focusing on analytic modeling of RRAM. In this article, modeling for solving analytic approximate solution to the state variable of RRAM, based on the proposed Multistage Homotopy Analysis Method (MuHAM), is proposed. Different from traditional HAM, the time span under consideration is divided into many subintervals, then the convergence control parameter in each subinterval is optimized to achieve high approximation accuracy. By simulating and comparing the obtained analytic solutions with solutions solved by other traditional homotopy-based modeling methodologies and by numerical analyses, we verified that MuHAM has higher Quality Factor (introduced to evaluate the model accuracy and computational cost comprehensively), hence improving the simulation efficiency. Besides the classical Hewlett-Packard (HP) RRAM, some current RRAMs are also verified. MuHAM also has the advantages of enabling both qualitative and quantitative analyses, and immunity to convergence issues. It is particularly suitable for the analytic modeling of the other novel memory devices having strong nonlinearity.

Memristive nonlinear system has drawn much attention in recent years, due to its rich and complex dynamical characteristics. However, there are few studies focus on the analytical analysis of this significant system. In this paper, a novel analytical method for analyzing the chaotic trajectories of memristive circuit is proposed. This method combines Homotopy Analysis Method (HAM) and Multi-objective Optimization (MO), i.e., the convergence control parameter of traditional HAM is divided into lots of subintervals in the time domain and respectively optimized by MO, for accurately solving the Ordinary Differential Equations describing memristive circuits. Hence, this method is named by MO-based multi-interval HAM (MO-MIHAM). By using MO-MIHAM, we accurately tracked the chaotic trajectories of the classical Memristor-Capacitor-Inductor (MCL) circuit and current memristive Band Pass Filter (BPF) chaotic circuit. Furthermore, based on the comparisons of errors between analytical approximate solutions derived from MO-MIHAM and solutions solved by traditional homotopy-based analytical methods and by Runge-Kutta-Fehlberg Method (RKF45) based numerical analysis, we found that, MO-MIHAM is characterized by higher approximation accuracy and computational performance (comprehensively considering the accuracy, computational complexity and execution time by a proposed Quality Factor) among the homotopy-based analytical methods, due to the optimized convergence control parameters in subintervals. Besides this major advantage, MO-MIHAM enables both qualitative and quantitative analyses and high freedom to choose homotopy-related terms for simplicity, and it is insensitive to convergence issues. Therefore, it is a powerful tool for exploratory studies for analytically analyzing chaotic dynamics in memristive circuit.

For the purpose of achieving the industrial requirement of efficient and high precision polishing of zirconia ceramics, nanodiamond@SiO2 abrasives were synthesized by a simple method using tetraethyl orthosilicate (TEOS) as raw materials. As observed in the transmission electron microscopy results, the composite abrasives showed a homogeneous and dense silica coating layer. It was confirmed by Fourier transform infrared spectroscopy and X-ray diffraction spectroscopy that the composite abrasives have a core–shell structure with a diamond core and a silica shell. According to the Zeta potential analysis, the dispersion stability of composite particles was improved compared to that of the pure nanodiamond particles. The chemical mechanical polishing (CMP) experimental results show that the polishing performances of composite abrasives on zirconia ceramics are better than that of the pure nanodiamond abrasives. The material removal rate of the composite particles is 2.184 μm h−1, and the surface roughness of the polished zirconia ceramics is 1.055 nm, which was 140% higher and 89% lower than that of pure nanodiamond abrasives, respectively. Furthermore, the polishing mechanism was explored by X-ray photoelectron spectroscopy (XPS), friction coefficient meter and dynamic contact angle test.

Being one of the world’s seismically hazard-prone countries, the People’s Republic of China (PRC) witnessed an 8.0-magnitude earthquake on May 12th 2008—which was reported as one of the most destructive disasters since its founding. Following this earthquake, rehabilitation was greatly required for survivors to enable them to achieve and maintain optimal independence; functioning; full physical, mental and social ability; inclusion; and participation in all aspects of life and environments. We conducted a systematic review based on Preferred Reporting Items for Systematic Reviews and Meta-Analyses (PRISMA) guidelines to retrospectively identify, in five English databases/sources, the existing evidence about the Health-Related Rehabilitation (HRR) that was rendered to the survivors of the 2008 Wenchuan earthquake between 2008 and 2018. Only 11 studies out of 828 initial studies retrieved were included in our study and reported the survivors of the 2008 Wenchuan earthquake to have been aged between 10.5 and 55.7, and predominantly diagnosed with posttraumatic stress disorders. Their HRR was mainly premised on physical and physiological therapies, as well as traditional Chinese medicine and digital technologies. Although all HRR interventions used were reported to be effective, none was identified as much more effective than the others in the post-earthquake era —which calls for more robust research to build upon our systematic review.

Scan testing is the key technology in the design for test of integrated circuit. For existing scan testing methods, the scan-in for test stimuli requires many clock cycles, which is one of the main restrictions of scan testing. To shorten the scan testing time of an integrated circuit, a novel test stimulus scan-in method was proposed in this study. First, scan chains, test stimuli, and test responses were grouped according to a fixed data width. Second, logic XOR calculation results of test response and test stimuli were coded according to the bit width of each group. The corresponding decoding and control circuits were added in the netlist of the circuit, which achieved fast input of test stimuli. Finally, an experiment using ISCA89 and IWLS2005 benchmark test circuits was performed. Experimental results were compared with those that used a serial input method of test stimuli. Results demonstrate that the proposed method can save approximately 37.5% and 43.7% of test time in average when the width of each group are 4 bits and 8 bits, respectively. The proposed method can decrease the clock cycles of scan testing significantly and shorten the scan testing time of the integrated circuit. Conclusions obtained in this study provide significant references for improving the scan testing method of digital integrated circuit. Keywords: Scan testing, Design for test, Test response, Test stimulus

Test vector coding and data transmission are the key technologies in the design-for-test of digital integrated circuits (IC). Existing parallel input methods of test stimuli can reduce test application times; however, they need to occupy multiple input ports. Thus, a novel method of test stimuli coding and data transmission was proposed to reduce the test application time of the test vectors and reduce the number of input ports required for the parallel input of test stimuli. This method was based on the segmentation of test stimuli. First, the test stimuli were evenly segmented into eight-bit wide. Second, the eight-bit data of each segment were encoded to the five-bit data according to the compatibility between the test data of each segment. The eight-bit test stimuli input can be completed in one or two clock cycles of automatic test equipment (ATE) by using the five input ports of the chip. The corresponding decoding circuit was added inside the netlist of the circuit to realize the rapid input of the test stimuli. Lastly, the ISCAS'89 benchmark circuit was used to conduct experiments, results of this coding method were then compared with those of the serial input method. Results show that the encoding method proposed in this study can save an average of 37% of the parallel input data width and 81.7% of the test stimuli input time. The proposed method in this study can also reduce the test application time and the cost of the IC test. The findings of this study can provide guidance for improving the scan testing method of digital IC.

Roll forming is an important processing method for the production of commercial vehicle anticollision beams, and edge buckling is one of the common defects in roll-forming process. In this paper, the “日” shape section of roll forming is studied, and first the b-shaped section is formed by roll forming, and the internal weld line is automatically welded while forming; then the long side of the b-shaped section is bent into the “U” shape, and the external weld line is welded while forming. The profile is cut off and then bent at both ends to form a commercial vehicle anticollision beam. The ABAQUS finite element software is used to model and analyze the factors affecting the “edge buckling” defect of roll-formed products. This paper uses three factors and three levels of orthogonal simulation experiments to study the problem. The results show that the effect of the factors of flange height, sheet thickness, and forming speed on the formation of edge buckling is in the order of sheet thickness > flange height > forming speed. The edge buckling size of the vertical edge of b-shaped tube decreases with the increase of sheet thickness and increases with the increase of flange height.

Springback is a common defect caused by elastic recovery in the plastic forming process, which can cause the formed workpiece to deviate from the target shape. The purpose of this paper is to grasp the influence law of process parameters on springback deviation so as to optimize process parameters to reduce springback. Taking the Y-profile as the research object, the influence of process parameters such as horizontal bending radius, vertical bending radius, transition zone length, radius of roller dies, and wall thickness of the profile on springback deviation is discussed by numerical simulation. Additionally, the validity of the numerical simulation is verified through experiments. The springback law obtained by numerical simulation is applied to practical production, and the large-scale production of the Y-profile is realized.

Special accelerator architecture has achieved great success in processor architecture, and it is trending in computer architecture development. However, as the memory access pattern of an accelerator is relatively complicated, the memory access performance is relatively poor, limiting the overall performance improvement of hardware accelerators. Moreover, memory controllers for hardware accelerators have been scarcely researched. We consider that a special accelerator memory controller is essential for improving the memory access performance. To this end, we propose a dynamic random access memory (DRAM) memory controller called NNAMC for neural network accelerators, which monitors the memory access stream of an accelerator and transfers it to the optimal address mapping scheme bank based on the memory access characteristics. NNAMC includes a stream access prediction unit (SAPU) that analyzes the type of data stream accessed by the accelerator via hardware, and designs the address mapping for different banks using a bank partitioning model (BPM). The image mapping method and hardware architecture were analyzed in a practical neural network accelerator. In the experiment, NNAMC achieved significantly lower access latency of the hardware accelerator than the competing address mapping schemes, increased the row buffer hit ratio by 13.68% on average (up to 26.17%), reduced the system access latency by 26.3% on average (up to 37.68%), and lowered the hardware cost. In addition, we also confirmed that NNAMC efficiently adapted to different network parameters.

Timing optimization for logic circuits is one of the key steps in logic synthesis. Extant research data are mainly proposed based on various intelligence algorithms. Hence, they are neither comparable with timing optimization data collected by the mainstream electronic design automation (EDA) tool nor able to verify the superiority of intelligence algorithms to the EDA tool in terms of optimization ability. To address these shortcomings, a novel verification method is proposed in this study. First, a discrete particle swarm optimization (DPSO) algorithm was applied to optimize the timing of the mixed polarity Reed-Muller (MPRM) logic circuit. Second, the Design Compiler (DC) algorithm was used to optimize the timing of the same MPRM logic circuit through special settings and constraints. Finally, the timing optimization results of the two algorithms were compared based on MCNC benchmark circuits. The timing optimization results obtained using DPSO are compared with those obtained from DC, and DPSO demonstrates an average reduction of 9.7% in the timing delays of critical paths for a number of MCNC benchmark circuits. The proposed verification method directly ascertains whether the intelligence algorithm has a better timing optimization ability than DC.

High precision and smart sensors make up an indispensable data entry for the Internet of Things technology. Nonetheless, conventional calibration algorithms mainly implemented on the software, such as least squares, polynomial fitting, and interpolation, exhibit limited calibration accuracy that does not reflect a real-time measurement of the sensors. The problem can be resolved with an MCU-based sensor calibration system proposed herein, which mainly employs particle swarm optimization (PSO)-back propagation (BP) neural network. The system firstly reads sensor data through I2C bus and then uses the BP neural network and PSO algorithm to automatically calibrate these data in real time. Sigmoid activation function was implemented via a piecewise polynomial fitting to create a trade-off between hardware resource and precision. A performance test conducted on temperature sensors showed a maximum error of 0.16 °C within the measurement range of −40–100 °C with three times the standard deviation (3 σ ) error of ±0.23 °C and overall linearity of 0.1143% after the calibration system was added as compared to the significantly higher error of ±0.63 °C without the calibration.

This work proposes a novel amplitude modulation topology which including a recently discovered unique memory element — memristor. The circuit is validated by theoretical analyses and simulations that generating a standard amplitude modulation signal with no harmonic component. Our results support the feasibility that memristor can be applied to communication circuit.

Based on the model of memeristor fabricated at HP laboratory, a new multiplexed flip-flop is proposed which can support power-off mode for scan testing. Testing data can be stored in memristor during the power-off time. The analyzes are verified with SPICE simulation, signal waveforms show that the presented memristive multiplexed flip-flop meet the requirements for low-power scan testing.

A CCD control system based on dsPIC Digital Signal Controller(DSC) which integrates two ADC modules is designed. As a result, the DSC device simplifies the circuit arrangement, reduces the cost and improves the compatibility of the CCD control system. CCD Work timing and ADC work timing are emphasized. The experimental results show the simplification and practicality through application of this CCD control system.