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There are many test challenges generated from at-speed delay testing requirements. BIST circuit can help to solve traditionally slower AT E tester problems. In this paper, a double edge clipping technique is proposed for at-speed BIST testing. It differs from traditional circuit delay testing techniques by changing the clock rate using external ATE. This method uses lower-speed input clock frequency, then applies internal BIST circuit to adjust clock edges for circuit at-speed delay testing and speed binning. Test chips are fully validated. The postlayout simulations that show that the wide-range (26%∼76%), fine-scale (16ps) duty cycle adjustment technique with high-precision (28ps) calibration circuit is effective for at-speed delay testing and performance binning.

The self wide-range (26%~76%), fine-scale (34ps) duty cycle adjustment technique with high-precision (28ps) calibration circuit are proposed for at-speed delay test and performance binning. Test chip DFT strategies are validated fully function work by instruments and HOY wireless test system.