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For the first time, the deformation caused by rapid thermal annealing (RTA) induced the mechanical stress has been observed visually. Based on the observation, a theoretical model has been derived to estimate the deformation caused by RTA. The model is then verified through chip implementation and measurement.

This paper investigates techniques for N-type high-resistance polysilicon resistors to reduce the resistance deviation which is caused by the back-end mechanical stress. In the back-end layers of the wafer, a top metal thickness equal to $3~\mu \text{m}$ is provided to increase the heat allowing current density in the metal routes of power ICs. The top metal processing yields the mechanical stress to increase the resistance by the piezoresistance effect. To eliminate the mechanical stresses, a new layout is proposed with the full passivation cutting (FPC). The resistor with an FPC uses the passivation film separation to create a physical empty room for suppressing the mechanical stresses on the polysilicon. The proposed layout has been verified in the 0.4- $\mu \text{m}$ bipolar-CMOS-DMOS process, and the resistance shifts were compared with other four-type layouts. Compared to those original layouts, the proposed layout exhibits the improvements in the resistance deviation reduction in the maximum ratio 20.80%.

This paper investigates power MOSFET stress strategies for both package and chip aging evaluation. Two stress test methods are developed to speed up packaging and chip aging process respectively. As a result, the characteristics shifts of package and chip aging can be plotted independently. Thus, the measurement accuracy and measurement time can be improved. A test chip is designed and fabricated in a 0.15μm BCD process. The measured results demonstrate a 10kμm power MOSFET has R on increased by 72% after 6.3hr stress for the package aging. For the chip aging, the MOSFET has R on increased by 12% after 600 times stress pulses. The measurement verifies that the accelerated aging in the package and the chip can be controlled separately.

A machine-learning (ML) assisted cardiac sensor SoC (CS-SoC) is designed for mobile healthcare applications. The heterogeneous architecture realizes the cardiac signal acquisition, filtering with versatile feature extractions and classifications, and enables the higher order analysis over traditional DSPs. Besides, the asynchronous architecture with dynamic standby controller further suppresses the system active duty and the leakage power dissipation. The proposed chip is fabricated in a 90-nm standard CMOS technology and operates at 0.5 V-1.0 V (0.7 V-1.0 V for SRAM and I/O interface). Examined with healthcare monitoring applications, the CS-SoC dissipates 48.6/105.2 μW for real-time syndrome detections of ECG-based arrhythmia/VCG-based myocardial infarction with 95.8/99% detection accuracy, respectively.

This paper presents a near-threshold low-power all-digital PLL (ADPLL). It includes a 9-bit bootstrapped DCO (BDCO) to reduce supply voltage and power consumption, a weighted thermometer-controlled resistor network (WTRN) to achieve high linearity, and a 4-bit sigma-delta modulator to improve the resolution through dithering. The ADPLL is fabricated in a 90 nm SPRVT low-K CMOS process with a core area of 0.057 mm2. The measured results demonstrate that the bootstrapped ring oscillator (BTRO) oscillates at 602 MHz under a supply of 0.5 V and consumes 49.1 μW. The ADPLL operates at 480 MHz (48 MHz) with a power consumption of 78 μW (2.4 μW) under a supply voltage of 0.5 V (0.25 V).

This paper presents an integrated transciver chip for use in electro-static coupling intra body communication. A simplified circuit model was developed to analyze the channel characteristics. A Manchester code was used to increase signal energy. In front of the receiver, an inverter-based amplifier applies to amplify the received data. Then, a Clock and Data Recovery data develops to recover the transmitted data. The chip is fabricated using UMC 0.18um CMOS process with a chip area of 0.75 × 0.7 mm2, power consumption of 22uW and a data transmission rate of 10M bit per second.

This work presents a biopotential front-end amplifier in which the MOS transistors are biased in subthreshold region with a supply voltage and current of 0.4-0.8 V and 0.23-1.86 μA, respectively, to reduce the system power. Flicker noise is then removed using a chopping technique, and differential interference produced by electrode impedance imbalance is suppressed using a Gm-C filter. Additionally, the circuit is fabricated using TSMC 0.18 μm CMOS technology with a core area of 0.77 × 0.36 mm2. With a minimum supply voltage of 0.4 V, the measured SNR and power consumption of the proposed IC chip are 54.1 dB and 0.09 μW , respectively.

This paper investigates the performance of the interconnects with repeater insertion in the subthreshold region. A 3X complementary metal-oxide-semiconductor (CMOS) predriver and a 4X one are proposed to enhance the driving capability. As compared to the conventional repeater, the proposed ones have higher energy efficiency. In addition, the results of Monte Carlo analysis indicate that the propose predrivers have higher concentration under the process and temperature variation than conventional one at 0.15 V. A test chip with 3X and 4X predrivers for 10-mm on-chip bus has been fabricated in 65 nm SPRVT CMOS process. The measured results show that the 3X (4X) predrivers can achieve 5 Mb/s (1.5 Mb/s) data rate at 0.15 V with an efficiency of 35.2 fJ (32.8 fJ).

This paper presents a 40-130 fJ/bit/ch on-chip data link design under a 0.1-0.3 V power supply. A bootstrapped CMOS repeater is proposed to drive a 10 mm on-chip bus. It features a -VDD to 2VDD swing to enhance the driving capability and reduces the sub-threshold leakage current. Additionally, a precharge enhancement scheme increases the speed of the data transmission, and a leakage current reduction technique suppresses ISI jitter. A test chip is fabricated in a 55 nm SPRVT Low-K CMOS process. The measured results demonstrate that for a 10 mm on-chip bus, the achievable data rate is 0.8-100 Mbps, and the energy consumption is 40-123 fJ per bit under 0.1-0.3 V VDD.

This paper proposes a cumulative DNL (CDNL) test methodology for the BIST of ADCs. It analyzes the histogram of the DNL of a predetermined k LSBs distance to determine the DNL and gain error. The advantage of this method over others is that the numbers of required code bins and required samples are significantly reduced. The simulation and measurements of a 12-bit ADC show that the proposed CDNL has an error of less than 5% with only 212 samples, which can only be achieved with 222 samples using the conventional method. It only needs 16 registers to store code bins in this experiment. key words: cumulative differential nonlinearity, gain error, jitter calibration, analog-to-digital converters (ADCs)

This brief presents a bootstrapped CMOS inverter operated with a subthreshold power supply. In addition to improving the driving ability, a large gate voltage swing from -VDD to 2VDD suppresses the subthreshold leakage current. As compared with other reported works, the proposed bootstrapped inverter uses fewer transistors operated in the subthreshold region. Therefore, our design has shorter delay time. The Monte Carlo analysis results indicate that a sigma of delay time is only 6.3 ns under the process and temperature variations with 200-mV operation. Additionally, a test chip is fabricated in the 90-nm SPRVT low-K CMOS process. Chip measurement results demonstrate the feasibility of operating ten-stage bootstrapped inverters with a 200-fF loading of each stage at 200-mV VDD. The test chip is able to achieve 10-MHz clock rate at 200 mV VDD, the power consumption is 1.01 μW, and the leakage power is 107 nW.

This paper presents a built-in jitter measurement approach for measuring the timing jitter of spread-spectrum clocks (SSCs) and a jitter estimation method for validating the approach. Because of the lack of dedicated measurement instruments for SSC timing jitter measurement, the jitter estimation method is proposed to correlate SSC and non-SSC jitter. A 1.2-GHz eight-phase SSC generator with the jitter measurement circuit is designed and fabricated using the 0.18-?m complementary metal-oxide-semiconductor technology. The measured results are validated by the proposed estimation method, which is the key contribution of this paper. The experimental results show that the proposed built-in measurement approach has an error of less than 0.0026 UI.

SUMMARY This study employs a simple measurement methodology that is based on the de-convolution of a square test stimulus to measure the transmission characteristics of the human body channel in an electrostaticcoupling intra body communication system. A battery-powered square waveform generator was developed to mimic the electrostatic-coupling intra body communication system operating in the environment of the ground free. The measurement results are then confirmed using a reliable measuring method (single tone) and spectral analysis. The results demonstrate that the proposed measurement approach is valid for up to 32.5 MHz, providing a data rate of over 16 Mbps.

In this study, we use the deconvolution of a square test stimulus to replace a series of sinusoidal test waveforms with different frequencies to simplify the measurement of human body impedance. The average biological impedance of body parts is evaluated by constructing a frequency response of the equivalent human body system. Only two stainless-steel electrodes are employed in the measurement and evaluation.

This paper presents an all-digital low-voltage-differential-signaling (LVDS) driver design for Serial Advanced Technology Attachment II. A simultaneous-switching-noise reduction technique and an autocalibration mechanism are implemented to suppress switching noise and to handle process and environmental variations. The circuit is implemented in a 0.18-mum 1P6M CMOS process with a core area of 0.072 mm2. At 3 Gbps, it consumes 9 mW of power under a 1.8-V power supply or 3 pJ/bit.

SUMMARY This study develops a form of digital baseband Intra-Body communication for wideband transmission. A simplified circuit model of signal and noise is constructed to analyze the contribution of the high pass filter function of the electrostatic coupling Intra-Body communication system to wideband digital transmission in electrostatic coupling Intra-Body communication. A unit step function is presented to determine the maximum high pass 3 dB pole that can ensure favorable signal quality in a baseband Intra-Body communication system. Body noise is measured to estimate the range of the high pass 3 dB pole with good Signal to Noise Ratio. A 3.3 Volt battery-powered FPGA is experimentally implemented to confirm the feasibility of the wideband Intra-Body communication system. The experimental results indicate that the digital baseband Intra-Body communication system supports a data rate of more than 16MPS.

This paper proposes a tree-topology multiplexer (MUX) that employs a multiphase low-frequency clock rather than a high-frequency clock. Analysis and simulation results show that the proposed design can achieve higher bandwidth and be less sensitive to process variations than the conventional single-stage MUX. In order to verify the feasibility, this proposed design is integrated with a multiphase phase-locked loop and a low-voltage differential signaling driver in a 0.18- mum CMOS technology. Measured results indicate that the proposed design can operate up to 7 gigabits/s under 0.3-UI jitter limitation.

A novel prediction scheme is proposed for real-time MPEG video to predict the burst and long-range dependent traffic. The trend and periodic characteristics of MPEG video traffic are fully captured by a proposed stochastic state-space dynamic model. Then a recursive Hinfin filtering algorithm is proposed to estimate traffic for long-range prediction. Simulation results based on real MPEG traffic data show that the proposed scheme has superior performance and lower complexity than some adaptive neural network methods, such as TDNN, NARX, and Elman neural networks.

A serial input-output (I/O) composed of inverters and transmission gates only is proposed to achieve high supply voltage scalability and low area overhead. The inverter with an inductive biasing circuit can extend bandwidth, and reduce the simultaneous switching noise simultaneously. With a TSMC 0.18-mum CMOS process, the I/O occupies an area of 0.014 mm2 and operates from 4 Gbps@1.9 V to 1.5 Gbps@1.1 V.

This paper presents a built-in self-test (BIST) circuit that measures the clock jitter of the charge-pump phase-locked loops (PLLs). The jitter-measurement structure is based on a novel time-to-digital converter (TDC) which has a high resolution. A small area overhead is also achieved using the voltage-controlled oscillator and the loop filter of the PLL under test as parts of the TDC. The experiment result shows that the resolution is about 1 ps and that the measurement error is smaller than 20%.

We propose a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two major issues are addressed. 1) The oscillation ring test (ORT) and its diagnosis scheme for interconnects based on the popular IEEE Standard 1500 are integrated into the multilevel routing framework to achieve testability enhancement. We augment the traditional multilevel framework of coarsening and uncoarsening by introducing a preprocessing stage that analyzes the interconnect structure for better resource estimation before the coarsening stage, and a final stage after uncoarsening that improves testability to achieve 100% interconnect fault coverage and maximal diagnosability. 2) We present a heuristic to reduce routing congestion to optimize the multiple-fault probability, chemical-mechanical polishing- and optical proximity correction-induced manufacturability, and crosstalk effects, for yield improvement. Experimental results on the Microelectronics Center for North Carolina benchmark circuits show that the proposed ORT method achieves 100% fault coverage and the optimal diagnosis resolution for interconnects. Further, the multilevel routing algorithm effectively balances the routing density to achieve 100% routing completion.

A novel oscillation ring (OR) test scheme and architecture for testing interconnects in SOC is proposed and demonstrated. In addition to stuck-at and open faults, this scheme can also detect delay faults and crosstalk glitches, which are otherwise very difficult to be tested under the traditional test schemes. IEEE Std. 1500 wrapper cells are modified to accommodate the test scheme. An efficient algorithm is proposed to construct ORs for SOC based on a graph model. Experimental results on MCNC benchmark circuits have been included to show the effectiveness of the algorithm. In all experiments, the scheme achieves 100% fault coverage with a small number of tests.

This paper presents a methodology based on congruent transformation for distributed interconnects described by state-space time-delays system. The proposed approach is to obtain the passive reduced order of linear time-delays system. The unified formulations are used to satisfy the passive preservation. The details of the mathematical proof and a couple of validation examples are given in this paper.

An interconnect diagnosis scheme based on the oscillation ring (OR) test methodology for systems-on-chip (SOC) design with heterogeneous cores is proposed. In addition to traditional stuck-at and open faults, the OR test can also detect and diagnose important interconnect faults such as delay faults and crosstalk glitches. The large number of test rings in the SOC design, however, significantly complicates the interconnect diagnosis problem. In this paper, the diagnosability of an interconnect structure is first analyzed then a fast diagnosability checking algorithm and an efficient diagnosis ring generation algorithm are proposed. It is shown in this paper that the generation algorithm achieves the maximum diagnosability for any interconnect. Two optimization techniques are also proposed, an adaptive and a concurrent diagnosis method, to improve the efficiency and effectiveness of interconnect diagnosis. Experiments on the MCNC benchmark circuits show the effectiveness of the proposed diagnosis algorithms. In all experiments, the method achieves 100% fault detection coverage and the optimal interconnect diagnosis resolution

In this work, IDDQ current for the deep sub-micron VLSI in year 2011 is estimated with a statistical approach according to the International Technology Roadmap for Semiconductors 1999 Edition considering process variations and different input vectors. The estimated results show that the standard deviation of the IDDQ current is proportional to the square root of the circuit size and the IDDQ currents of the defect-free and the defective devices, which are of the size up to 1 × 107 gates, are still differentiable under the condition of random process deviations and input vectors. Two new IDDQ testing schemes, which detect the defective current based on the two separate IDDQ distributions, are proposed. From the study, it is concluded that IDDQ testing is still applicable for the deep sub-micron VLSI for the next ten years.

A parasitic effect removal methodology is proposed to handle the large parasitic effects in analog testability buses. The removal is done by an on-chip test generation technique and an intrinsic response extraction algorithm. On-chip test generation creates test signals on-chip to avoid the parasitic effects of the test application bus. The intrinsic response extraction cross-checks and cancels the parasitic effects of both test application and response observation paths. The tests using both SPICE simulation and MNABST-1 P1149.4 test chip reveal that the proposed algorthm can not only remove the parasitic effects of the test buses but also tolerate test signal variations. Furthermore, it is robust enough to handle loud environmental noise and the nonlinearity of the switching devices.

This paper presents a novel scheme to diagnose single and double faults for linear analog circuits. The scheme first proposes a simple transformation procedure to transform the tested linear analog circuit into a discrete signal flow graph, then constructs “diagnosing evaluators,” which model the faulty components, to form a diagnosis configuration to diagnose the faults through digital simulation. This saves much computation time. Furthermore, a simple method to un-power OP's is also proposed to differentiate equivalent faults. The scheme can diagnose faults in passive components as well as active faults in OP's.

The removal of the parasitic effects is an emerging issue in the implementation of the IEEE standard 1149.4 analog test buses. For this, this paper defines the intrinsic response and derives an extraction algorithm. The intrinsic response is defined as the response of the circuit being tested by an ideal input signal without the parasitic effect. A deconvolution process is proposed to extract the intrinsic response from the response contaminated by the parasitic effects. The test results using SPICE simulation data show that the intrinsic responses remain the same regardless of the differences in the parasitic effects and the variations in the test signals. The proposed methodology is further tested in the real measurement using the MNABST-1 test chip designed by Matsushita/Panasonic and provided by 1149.4 Working Group. The test results show that the intrinsic response has an improvement of 15.4 dB in signal-to-noise ratio as compared to the direct measurement. It also extends the test frequency range by an order of magnitude. Both tests reassert that the intrinsic response is independent of parasitic effects and input signal variation. They also show that the proposed extraction algorithm is robust enough to handle not only the parasitic effects but also the noise in the real measurement environment.

This paper presents an architecture for the local generation of global test vectors for interconnects in a multiple scan chain environment. A unified BIST module is inserted as the gateway for each scan chain to transform the hierarchy of backplane, boards, and scan chains into a one-dimensional array of scan chains. The BIST modules are identical for all the scan chains except for the programmable personalized memories. The personalized memory contains a scan stage type table for the test generation, response compression, and driver contention avoidance. It also contains a scan chain identification number which serves as the seed for the generation of globally distinct serial vectors. The proposed methodology achieves 100% coverage on stuck-at and short faults.

This paper proposes a new pipelined full-adder circuit structure for the implementation of pipelined arithmetic modules. With both static and dynamic structures, it has the advantages of high operational speed, smallest transistor count, and the low power/speed ratio. The adder cell is then used to design a pipelined 8/spl times/8-b multiplier-accumulator (MAC). In this MAC, a special pipelined structure is designed to reduce the latency. The MAC is fabricated in a 0.8-/spl mu/m single-poly-double-metal CMOS process. The post-layout simulation shows that the pipelined 1-b full adder can work up to 350 MHz with a 3 V power supply. The whole MAC chip that contains 4200 transistors is measured to operate a 125 MHz using 3.3 V power supply.

This work presents a biopotential front-end amplifier in which the MOS transistors are biased in subthreshold region with a supply voltage and current of 0.4-0.8 V and 0.23-1.86 μA, respectively, to reduce the system power. Flicker noise is then removed using a chopping technique, and differential interference produced by electrode impedance imbalance is suppressed using a Gm-C filter. Additionally, the circuit is fabricated using TSMC 0.18 μm CMOS technology with a core area of 0.77 × 0.36 mm². With a minimum supply voltage of 0.4 V, the measured SNR and power consumption of the proposed IC chip are 54.1 dB and 0.09μW, respectively.

Background Intra-body communication is a new wireless scheme for transmitting signals through the human body. Understanding the transmission characteristics of the human body is therefore becoming increasingly important. Electrostatic-coupling intra-body communication system in a ground-free situation that integrate electronic products that are discretely located on individuals, such as mobile phones, PDAs, wearable computers, and biomedical sensors, are of particular interest. Materials and Methods The human body is modeled as a simplified Resistor-Capacitor network. A virtual ground between the transmitter and receiver in the system is represented by a resister-capacitor network. Value of its resistance and capacitance are determined from a system perspective. The system is characterized by using a mathematical unit step function in digital baseband transmission scheme with and without Manchester code. As a result, the signal-to-noise and to-intersymbol-interference ratios are improved by manipulating the load resistor. The data transmission rate of the system is optimized. A battery-powered transmitter and receiver are developed to validate the proposal. Results A ground-free system fade signal energy especially for a low-frequency signal limited system transmission rate. The system transmission rate is maximized by simply manipulating the load resistor. Experimental results demonstrate that for a load resistance of 10k−50k Ω, the high-pass 3 dB frequency of the band-pass channel is 400kHz−2MHz in the worst-case scenario. The system allows a Manchester-coded baseband signal to be transmitted at speeds of up to 20M bit per second with signal-to-noise and signal-to-intersymbol-interference ratio of more than 10 dB. Conclusion The human body can function as a high speed transmission medium with a data transmission rate of 20Mbps in an electrostatic-coupling intra-body communication system. Therefore, a wideband signal can be transmitted directly through the human body with a good signal-to-noise quality of 10 dB if the high-pass 3 dB frequency is suitably selected.

This paper presents a bootstrapped inverter based ring oscillator for 0.2–0.6V operation. The proposed delay cell provides a boosted voltage swing to enhance the driving capability and suppress the large process variation in the low-voltage region. As compared with conventional inverter-based ring oscillators, the proposed one provides better linearity when controlled by the supply voltage. A test chip is fabricated in 90 nm SPRVT Low-K CMOS process. The measured results demonstrate that the proposed bootstrapped ring oscillator oscillates at 48MHz (771MHz) with a power consumption of at 0.63μW (87.6μw) and a phase noise of −93dBc/Hz (−88.5dBc/Hz) at a 1-MHz offset under a supply voltage of 0.2V (0.6V) V DD .

This work develops automatic gain control (AGC) system based on a low power and low area mix mode for the front-end circuitry of a hearing aid. By incorporating a direct feedback method for the sigma-delta modulator output without a decimation filter, the proposed AGC system can reduce the chip area, latency and system power consumption. Additionally, an operational transconductance amplifier (OTA) based on an inverter structure of the CMOS transistor is developed to design a sigma-delta modulator in order to decrease system power consumption. Moreover, a novel algorithm is also developed by rectifying the output bit stream of the sigma-delta modulator to detect the average waveform of the proposed AGC system. The proposed AGC system is implemented using TSMC 0.18 μm CMOS technology with an IC chip area of 600×680 μm 2 . Furthermore, the system power consumption is 42.3 μW with a DC supply voltage of 1 V. Measurement results verify that the proposed system can implement an IC chip that capable of providing a digital output signal of 6 bits, which is feasible for hearing aid systems.

This paper presents an on-chip pulse signaling scheme for low power on-chip interconnection. Both near-end and far-end employ equalization circuits to compensate the high frequency attenuation of long channel. The on-chip data bus is designed by co-planar micro-strip line in Metal 5 and Metal 6 and with a characteristic impedance of 75 ohm. The receiver uses self-biased inverters and transmission gates to design inductive-peaking and non-clock hysteresis amplifiers. In 0.13um CMOS process, the proposed I/O occupies a total area of 0.07mm2. At a bit rate of 5Gbps, the accumulated peak-to-peak jitter of overall I/O system and a 5mm of channel length is 76ps. And it consumes 8mW of power under 1.2V supply voltage or with a power efficiency of 0.32pJ/bit/mm.

This paper presents a programmable analog front-end IC for multiple biomedical signal acquisition. By chopper-stabilized technique with an AC feedback circuit, the proposed circuit rejects differential electrode offset, common-mode disturbance and solves the problem of flicker noise. In TSMC 0.18µm CMOS process, the proposed circuit occupies an active area of 0.38mm2. With digital controls, the voltage gain, low-pass and high-pass cutoff frequency could be adjusted in the range of 52db–88db, 0.5Hz–10Hz and 100Hz–400Hz, respectively. With a supply voltage of 1.5V, the proposed circuit achieves an input-referred noise of 90nV∗Hz⁁−0.5, a noise-efficient factor of 6.1 while consuming a total current of 5µA.

In this paper, a micro-network on chip (MNoC) with 10-Gb/s transmission link is proposed. A prototype system with two 5-port packet-based on-chip micro-switches and a 10-Gb/s data transceiver with an all digital data recovery circuit and a self-calibration clock generator are designed. This chip is implemented in 0.13μm CMOS technology. The core area of this chip is 990μm∗1600μm and the power consumption is 155mW (60mW for micro-switches and 95mW for 10-Gb/s data transceiver) at 1.2V supply voltage with 10-Gb/s transmission data rate.

Estimator which guarantee Hinfin robustness performance for the considered nonlinear stochastic systems can be obtained by solving bilinear matrix inequalities. Then, to solve the bilinear matrix inequalities, a two-stage method is adopted to separately obtain the controller gain matrices and the estimator gain matrices by solving two sets of linear matrix inequalities. An example is given to verify the derived results.

In this paper, a built-in-self-test methodology for measuring frequency deviation and jitter of spread-spectrum clock generators is presented. It utilizes a phase detector to detect the clock phase of spread spectrum clock (SSC) and then measure the jitter by filtering out the low frequency component of the clock phase. Frequency of spread-spectrum clock can also be obtained by filtering out the high frequency component of the signal. The methodology is analyzed and verified with chip implementation and measurement. As an all digital design, the hardware overhead is very low.

Publisher Summary Analog and mixed-signal (AMS) circuits are becoming more critical in the system on- chip (SOC) era, although they are occupying less silicon area. AMS circuits are designed using specialized techniques because a wide range of circuit structures are possible. This chapter introduces AMS circuits, failure modes, and fault models. It then addresses analog testing, including DC and AC parametric testing. Waveform-oriented testing and specification-oriented testing are reviewed in the chapter. Then, mixed-signal circuits, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and their testing approaches, are discussed. This chapter also illustrates that, terminology and test approaches are consistent with the IEEE 1057 standard. Finally, the IEEE 1149.4 standard for mixed-signal test buses is studied. Two analog test buses are employed to deliver test stimuli and test responses in board-level analog interconnect testing and passive component measurement.

This paper presented an inverter based 3rd order sigma-delta ADC. Cascode structure and auto-zeroing mechanism are proposed for the gain enhancement and offset cancellation. The ADC has been implemented in TSMC 2P6M 0.18 μm CMOS technology with a core area of 0.54 mm2. The measurement results show that for the 1-V supply, 20-KHz bandwidth, and 2-MHz sampling rate, the power consumption is 42 μW and the dynamic range of 66.02 dB.

A novel multi-phase tree type multiplexer is proposed. It has the speed of the tree type multiplexer while operates at the clock rate of the multi-phase type multiplexer. The transmitter is implemented in 0.18 digital CMOS technology. It operates at the rate of 1.25Gbps to 5Gbps. The jitter is measured at 61ps at 5Gbps. The transmitter occupies an area of 300mum times 300mum and consumes 69.6mW of power

This paper presents an all digital low voltage differential signal (LVDS) driver for serial-ATA (SATA-II) with simultaneous switching noise (SSN) reduction capability. An auto calibration mechanism is included to deal with the process and environmental variation. The chip is implemented using TSMC 0.18-mum 1P6M CMOS technology. The core area is 350times350 mum2. The transmitter operates at 3 Gbps under a 1.8V power supply and consumes 11mW of power

In this paper, we proposed a spread spectrum clock generator (SSCG) for the Serial AT Attachment Generation 2 (SATA-II). We use a fractional-N PLL to accomplish the spread spectrum function. The SSCG integrates a conventional PLL, a digital 3/sup rd/ order MASH 1-1-1 delta-sigma modulator and an address generator. The SSCG generates clocks at 1.5 GHz, a 5000 ppm down spread with a triangular waveform frequency modulation of 33 kHz. The circuit has been simulated in 0.18 /spl mu/m CMOS technology. The non spread spectrum clocking has a jitter of 80 ps and the peak amplitude reduction is 23.44 dBm in spread spectrum mode. The power dissipation from a 1.8 V supply is 55 mW.

A dynamic analog test methodology using digital tester is proposed. A simple triangular waveform is built on the device interface board for the stimulus generation. The response waveform is quantized by the dual comparators in a digital pin electronic circuit. Statistical analysis is conducted to enhance the quantization resolution and minimize the noise effect. The experimental results using an ATE show that the error is less than 2%. It confirms the feasibility of the proposed methodology.