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BACKGROUND: Chronic respiratory diseases (CRDs) are considered a significant cause of morbidity and mortality worldwide, although data from Africa are limited. This study aimed to determine the prevalence and determinants of CRDs in Khartoum, Sudan.METHODS: Data were collected from 516 participants aged ≥40 years, who had completed a questionnaire and undertook pre- and post-bronchodilator spirometry testing. Trained field workers administered the questionnaires and conducted spirometry. Survey-weighted prevalence of respiratory symptoms and spirometric abnormalities were estimated. Regression analysis models were used to identify risk factors for chronic lung diseases.RESULTS: Using the Third National Health and Nutrition Examination Survey, 1988–1994 (NHANES III) reference equations, the prevalence of chronic airflow obstruction (CAO) was 10%. The main risk factor was older age, 60–69 years (OR 3.16, 95% CI 1.20–8.31). Lower education, high body mass index and a history of TB were also identified as significant risk factors. The prevalence of a low forced vital capacity (FVC) using NHANES III was 62.7% (SE 2.2) and 11.3% (SE 1.4) using locally derived values.CONCLUSION: The prevalence of spirometric abnormality, mainly low FVC, was high, suggesting that CRD is of substantial public health importance in urban Sudan. Strategies for the prevention and control of these problems are needed.

Hardware inefficiency of neural synapse multiplication has placed an upper limit on the neural network size that can be implemented on a single FPGA. In this paper, we make use of distributed arithmetic and internal lookup tables of FPGA structures to improve the efficiency of synapse multiplication. We propose a weight clustering optimization method to further reduce area requirements of the target hardware. Applying our proposed method to a sample neuron, we were able to reduce the hardware requirements of synapse multiplier by 30%. Our parameterized approach can be utilized for automation of neural network synthesis onto FPGA devices.

Steady FPGA density and speed improvement in recent years has paved the path for realization of larger Neural Networks On a Programmable Chip (NNOPC), a high performance and low cost alternative to traditional physical implementations of artificial neural networks. In this paper, we propose a parametric approach for mapping artificial neural networks onto FPGA structures, as well as an optimization method to reduce area requirements of the synthesized hardware. Applying this method to a sample neuron, we achieved a 30% reduction in hardware resource requirements of the synaptic multiplier.